IP Library Granted Patent US 7,218,119
Granted Patent B1
US 7,218,119 · App. 11/444,087 · Granted May 15, 2007

System and method for reducing current in a device during testing

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Quick Facts
Patent No.
US 7,218,119
App. No.
11/444,087
Granted
May 15, 2007
Kind
B1
Abstract

A method for testing an electronic assembly ( 10 ) is provided. A portion ( 22 ) of the electronic assembly is electrically isolated from a remainder ( 24 ) of the electronic assembly. Power is provided to the electronic assembly such that a reduced amount of current flows only through the portion of the electronic assembly. The reduced amount of current is determined. A combined amount of current flowing through both the portion and the remainder of the electronic assembly when power is provided to both the portion and the remainder of the electronic assembly is calculated based on the reduced amount of current.

Claims (16)

1. A method for testing an electronic device comprising a plurality of transistors, the method comprising:

electrically isolating a portion of the electronic device from a remainder of the electronic device, a portion of the plurality of transistors being within the portion of the electronic device and a remainder of the plurality of transistors being within a remainder of the electronic device;

providing power to the electronic device such that a reduced amount of control current only flows through the portion of the electronic device;

determining the reduced amount of control current, said determination of the reduced amount of control current comprising providing power to the portion of the electronic device such that current flows through the portion of the plurality of transistors and determining a test amount of control current flowing through at least one selected transistor of the portion of the plurality of transistors, the portion of the plurality of transistors being less than 50 percent of the plurality of transistors and the at least one selected transistor being less than 10 percent of the portion of the plurality of transistors; and

calculating a combined amount of control current flowing through both the portion and the remainder of the electronic device when power is provided to both the portion and the reminder of the electronic device based on the reduced amount of control current, wherein the reduced amount is less than 50 percent of the combined amount of control current.

2. The method of claim 1 , wherein the electronic device is configured such that the reduced amount of current is a predetermined percentage of the combined amount of current.

3. The method of claim 2 , wherein the portion of the electronic device and the portion of the plurality of transistors are configured such that the test amount of current is a predetermined percentage of the reduced amount of current.

4. The method of claim 3 , wherein the test amount of current, the reduced amount of current, and the combined amount of current are control currents for the electronic device, the portion of the electronic device, and the at least one selected transistor, respectively.

5. The method of claim 1 , wherein the electronic device includes a microelectronic die with an integrated circuit formed thereon.

6. A method for testing a microelectronic assembly comprising:

providing power to a plurality of transistors in the microelectronic assembly such that current flows through the plurality of transistors;

electrically isolating a predetermined number of the plurality of transistors, the predetermined number of the plurality of transistors being less than 50 percent of the plurality of transistors;

providing power to the predetermined number of the plurality of transistors such that current flows through only the predetermined number of the plurality of transistors;

determining a reduced control current for the predetermined number of the plurality of transistors, said determination of the reduced control current comprising providing power to the predetermined number of the plurality of transistors such that current flows through the predetermined number of the plurality of transistors and determining a test control current flowing through at least one selected transistor of the predetermined number of the plurality of transistors and is based on the test control current, the at least one selected transistor being less than 10 percent of the predetermined number of the plurality of transistors; and

calculating a total control current for the plurality of transistors based on the reduced control current for the predetermined number of the plurality of transistors, wherein the microelectronic assembly is configured such that the reduced control current is a predetermined percentage of the total control current and the test control current is a predetermined percentage of the reduced control current.

7. The method of claim 6 , wherein the microelectronic assembly is a power integrated circuit and includes a microelectronic die, the plurality of transistors being formed on the microelectronic die.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0655 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →