Compact non-volatile memory array with reduced disturb
View Patent ↗A non-volatile memory (NVM) array is made of NVM cells that have a floating gate transistor and a select transistor in which the floating gate transistor requires only a single layer of polysilicon. Adjacent cells are arranged so that the floating gates are staggered rather than being in the same line. This results in being able to put the cells closer together because of the reduction of the significance of what is commonly called poly-to-poly spacing. In this case, the termination of one floating gate is not lined-up with the floating gate of the adjacent NVM cell in the same row. Adjacent memory cells in the same column are made to have different configurations from each other which results in the floating gates in adjacent columns not being aligned, thus avoiding the poly-to-poly spacing limitation.
1. A nonvolatile memory array comprising:
a plurality of memory cells arranged in rows and columns, each row comprising a corresponding one of a plurality of word lines and each column comprising two of a plurality of bit lines, each memory cell comprising:
a select transistor having a first current electrode, a control electrode connected to a predetermined one of the plurality of word lines corresponding to a respective row and a second current electrode connected to a predetermined first of the two of the plurality of bit lines corresponding to a respective column; and
a floating gate transistor having a first current electrode connected to the first current electrode of the select transistor, a floating gate, and a second current electrode connected to a predetermined second of the two of the plurality of bit lines corresponding to the respective column;
the second current electrode of the select transistor of a first memory cell and the second current electrode of the floating gate transistor of a second memory cell in an adjacent column cell location of a same column are directly connected to a same bit line.
2. The nonvolatile memory array of claim 1 wherein the select transistor and the floating gate transistor of adjoining memory cells in a row having a substantially same physical layout.
3. The nonvolatile memory array of claim 1 wherein the select transistor and the floating gate transistor of adjoining memory cells in a column have a substantially mirrored physical layout.
4. The nonvolatile memory array of claim 1 wherein the floating gate of the floating gate transistor of the first memory cell is not laterally aligned with a floating gate of a floating gate transistor of a third memory cell which is adjacent the first memory cell in a same row, and a separation distance between adjacent columns is reduced.
5. The nonvolatile memory array of claim 4 wherein a perpendicular axis through an edge of the floating gate of the floating gate transistor of the first memory cell intersects the floating gate of the floating gate transistor of the third memory cell wherein the floating gate of the floating gate transistor of the first memory cell laterally overlaps but does not physically contact the floating gate of the floating gate transistor of the third memory cell.
6. The nonvolatile memory array of claim 1 wherein the floating gate of the floating gate transistor of the first memory cell is at least partially laterally aligned with at least a portion of a contact to a bit line of a third memory cell which is adjacent the first memory cell in a same row, wherein a select transistor of the third memory cell is connected to said contact to the bit line of the third memory cell.
7. The nonvolatile memory array of claim 1 further comprising:
a third memory cell which is adjacent the first memory cell in a same row and an adjacent column and coupled to a third bit line and a fourth bit line, the third bit line being closer to the first memory cell than the fourth bit line, the third memory cell comprising a respective select transistor having a current electrode directly connected to the third bit line and a respective floating gate transistor having a current electrode directly connected to the fourth bit line.
8. The nonvolatile memory array of claim 1 further comprising:
a third memory cell which is adjacent the first memory cell in a same row and an adjacent column and coupled to a third bit line and a fourth bit line, the third bit line being closer to the first memory cell than the fourth bit line, the third memory cell comprising a respective floating gate transistor having a current electrode directly connected to the third bit line and a respective select transistor having a current electrode directly connected to the fourth bit line.
9. The nonvolatile memory array of claim 1 wherein each column of the plurality of memory cells comprises two of the plurality of bit lines by sharing a common bit line with each adjoining column.
10. A nonvolatile memory array having a plurality of memory cells arranged in rows and columns, comprising:
a first continuous active area defining a first column;
a second continuous active area defining a second column and separated from the first continuous active area by a separation area of a predetermined minimum distance;
a first word line orthogonal to and above the first continuous active area and the second continuous active area and within a first row;
a second word line orthogonal to and above the first continuous active area and the second continuous active area and within a second row;
a first memory cell formed overlying the first continuous active area and having a first floating gate electrode on a first side of the first word line; and
a second memory cell laterally adjacent the first memory cell within the first row and formed overlying the second continuous active area and having a second floating gate electrode positioned on an opposing side of the first word line than the first floating gate electrode;
wherein each of the first floating gate electrode and the second floating gate electrode extend laterally into the separation area by a distance greater than fifty percent of the separation area and without touching.
11. The nonvolatile memory array of claim 10 further comprising:
a first contact structure in the second memory cell in the second area and on the first side of the first word line; and
a second contact structure in the first memory cell in the first area and on the second side of the first word line.
12. A method of providing a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, comprising:
providing two bit lines per column;
providing a select transistor in each memory cell, the select transistor having a first current electrode, a control electrode connected to a predetermined one of the plurality of word lines corresponding to a respective row, and a second current electrode connected to a predetermined first of the two of the plurality of bit lines corresponding to a respective column;
providing a floating gate transistor in each memory cell, the floating gate transistor having a first current electrode connected to the first current electrode of the select transistor, a floating gate, and a second current electrode connected to a predetermined second of the two of the plurality of bit lines corresponding to the respective column; and
directly connecting the second current electrode of the select transistor of a first memory cell and the second current electrode of the floating gate transistor of a second memory cell in an adjacent column cell location of a same column to a same bit line.
13. The method of claim 12 further comprising:
forming the select transistor and the floating gate transistor of adjoining memory cells in a row with a substantially same physical layout.
14. The method of claim 12 further comprising:
wherein the select transistor and the floating gate transistor of adjoining memory cells in a column have a substantially mirrored physical layout.
15. The method of claim 12 further comprising:
laterally misaligning the floating gate of the floating gate transistor of the first memory cell with a floating gate of a floating gate transistor of a third memory cell which is adjacent the first memory cell in an adjacent row, the misaligning allowing reduction of a separation distance between adjacent columns.
16. The method of claim 15 further comprising extending the floating gate of the floating gate transistor of the first memory cell and the floating gate of the floating gate transistor of the third memory cell into the separation distance.
17. The method of claim 12 further comprising:
partially laterally aligning the floating gate of the floating gate transistor of the first memory cell with at least a portion of a contact to a bit line of a third memory cell which is adjacent the first memory cell in an adjacent row.
18. The method of claim 12 further comprising:
providing a third memory cell adjacent to the first memory cell in a same row and an adjacent column and coupled to a third bit line and a fourth bit line, the third bit line being closer to the first memory cell than the fourth bit line, the third memory cell comprising a respective select transistor having a current electrode directly connected to the third bit line and a respective floating gate transistor having a current electrode directly connected to the fourth bit line.
19. The method of claim 12 further comprising:
providing a third memory cell which is adjacent the first memory cell in a same row and an adjacent column and coupled to a third bit line and a fourth bit line, the third bit line being closer to the first memory cell than the fourth bit line, the third memory cell comprising a respective floating gate transistor having a current electrode directly connected to the third bit line and a respective select transistor having a current electrode directly connected to the fourth bit line.