Semiconductor structure and method of assembly
View Patent ↗A semiconductor structure ( 100, 900 ) includes a substrate ( 110 ) having a surface ( 111 ) and also includes one or more semiconductor chips ( 120 ) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure ( 340 ) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads ( 341, 342 ) and an organic-based element ( 343 ) molded to the electrical leads. The semiconductor structure also includes a solder element ( 350 ) coupling together the electrical isolator structure and the substrate surface.
1. A semiconductor structure comprising:
a substrate having a first surface;
a semiconductor chip located over the first surface of the substrate;
an electrical isolator structure located over the first surface of the substrate, wherein the electrical isolator structure comprises an electrical lead and an organic-based element molded to the electrical lead; and
a solder element coupling together the electrical isolator structure and the first surface of the substrate,
wherein:
the electrical isolator structure further comprises a metal element;
the organic-based element is molded to the metal element; and
the organic-based element is located between the metal element and the electrical lead.
2. The semiconductor structure of claim 1 wherein:
the substrate is comprised of an electrically conductive material and is electrically coupled to the semiconductor chip.
3. The semiconductor structure of claim 1 wherein:
the metal element has a solderable surface facing towards the solder element; and
the solder element is soldered to the solderable surface of the metal element.
4. The semiconductor structure of claim 1 wherein:
the metal element is located between the solder element and the electrical lead and between the solder element and the organic-based element.
5. The semiconductor structure of claim 1 wherein:
the organic-based element electrically insulates the electrical lead from the metal element.
6. The semiconductor structure of claim 1 wherein:
the metal element has a surface facing towards the substrate and having a first surface area;
the organic-based element has a surface facing towards the substrate and having a second surface area; and
the first surface area is less than the second surface area.
7. The semiconductor structure of claim 6 wherein:
a portion of the second surface area is a solder dam for the solder element.
8. The semiconductor structure of claim 1 further comprising:
an adhesive located between and coupling together the semiconductor chip and the first surface of the substrate,
wherein;
the solder element has a first melting temperature; and
the adhesive has a second melting temperature less than the first melting temperature.
9. A semiconductor packaging system comprising:
a flange comprised of an electrically conductive material and having a first surface;
at least one semiconductor chip having at least one semiconductor device located over and electrically coupled to the first surface of the flange, wherein the at least one semiconductor device is an active device;
at least one matching element located over the first surface of the flange;
a first solder element coupling the at least one semiconductor device to the first surface of the flange, wherein the first solder element comprises a lead-free solder;
a frame structure located over the first surface of the flange, wherein the frame structure comprises at least two electrical leads, a base metal element located under the at least two electrical leads, and an organic-based, electrically insulative element located between and molded to the at least two electrical leads and the base metal element;
a second solder element coupling the base metal element to the first surface of the flange; and
electrical interconnect structures electrically coupling the at least one semiconductor device and the at least one matching element to the at least two electrical leads; and
a lid located over the flange and the frame structure to at least gross leak seal the at least one semiconductor chip, the at least one matching element, and the electrical interconnect structures therein.
10. The semiconductor packaging system of claim 9 wherein:
the flange is a third electrical lead for the at least one semiconductor device; and
the flange further comprises a metal layer overlying the electrically conductive material, wherein the metal layer comprises a solderable surface comprised of nickel and gold.
11. The semiconductor packaging system of claim 10 wherein:
the base metal element comprises a solderable surface; and
the second solder element is soldered to the solderable surface of the base metal element and the solderable surface of the flange.
12. The semiconductor packaging system of claim 9 wherein:
a surface of the organic-based, electrically insulative element facing towards the flange has a first surface area; and
a surface of the base metal element facing towards the flange has a second surface area less than the first surface area.
13. The semiconductor packaging system of claim 12 wherein:
the surface of the base metal element covers a first portion of the surface of the organic-based, electrically insulative element;
the surface of the base metal element is absent over a second portion of the surface of the organic-based, electrically insulative element; and
the second portion of the surface of the organic-based, electrically insulative element is a solder dam for the second solder element.
14. The semiconductor packaging system of claim 9 wherein:
the base metal element has at least one mold locking feature.
15. The semiconductor packaging system of claim 9 wherein:
the first solder element has a first melting temperature; and
the second solder element has a second melting temperature less than the first melting temperature.
16. The semiconductor packaging system of claim 15 further comprising:
a circuit board; and
a third solder element electrically coupling the at least two electrical leads to the circuit board,
wherein:
the third solder element has a melting temperature less than the second melting temperature.
17. The semiconductor packaging system of claim 9 wherein:
the flange, the frame structure, the second solder element, and the lid form at least a portion of a high power, radio frequency package having an air gap in which the at least one semiconductor chip, the at least one matching element, and the electrical interconnect structures are located.
18. The semiconductor packaging system of claim 9 wherein:
the flange comprises:
an electrically conductive material comprised of copper; and
a solderable metal layer comprised of nickel and gold;
the first solder element comprises gold and silicon;
the at least two electrical leads comprise:
an electrically conductive material comprised of a material selected from the group consisting of copper, nickel, and iron;
the base metal element comprises:
an electrically conductive material comprised of a material selected from the group consisting of copper, nickel, and iron; and
a solderable metal layer comprised of gold and tin;
the organic-based, electrically insulative element comprises a polymer; and
the second solder element comprises gold and tin.
19. The semiconductor packaging system of claim 9 wherein:
the base metal element and the at least two electrical leads are comprised of substantially similar materials.
20. A semiconductor structure comprising:
a substrate having a first surface;
a semiconductor chip located over the first surface of the substrate;
an electrical isolator structure located over the first surface of the substrate, wherein the electrical isolator structure comprises an electrical lead and an organic-based element; and
a solder element coupling together the electrical isolator structure and the first surface of the substrate,
wherein:
the organic-based element comprises a plastic; and
the electrical isolator structure further comprises a metal element.
21. The semiconductor structure of claim 20 wherein:
the substrate comprises an electrically conductive material and is electrically coupled to the semiconductor chip.
22. A semiconductor structure comprising:
a substrate having a first surface;
a semiconductor chip located over the first surface of the substrate;
an electrical isolator structure located over the first surface of the substrate, wherein the electrical isolator structure comprises an electrical lead and an organic-based element; and
a solder element coupling together the electrical isolator structure and the first surface of the substrate;
an adhesive located between and coupling together the semiconductor chip and the first surface of the substrate,
wherein:
the solder element has a first melting temperature; and
the adhesive has a second melting temperature less than the first melting temperature; and
the organic-based element comprises a plastic.
23. The semiconductor structure of claim 20 wherein:
the organic-based element is located between the metal element and the electrical lead.
24. The semiconductor structure of claim 20 wherein:
the metal element comprises mold locks; and
the organic based element is molded to the mold locks of the metal element and the electrical lead.
25. The semiconductor structure of claim 20 wherein:
the organic-based element comprises one of a plastic polymer, a thermoplastic, and a thermoset plastic.
26. The semiconductor structure of claim 20 wherein:
the organic-based element is located between the electrical lead and the substrate.
27. The semiconductor structure of claim 22 wherein:
the substrate is comprised of an electrically conductive material and is electrically coupled to the semiconductor chip.