Process of forming an electronic device including a resistor-capacitor filter
View Patent ↗A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.
1. A process of forming an electronic device comprising:
forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material;
forming a gate dielectric layer over a substrate,
forming a capacitor electrode over the capacitor dielectric layer;
forming a gate electrode over the gate dielectric layer;
forming a field isolation region to define a first active area and a second active area, wherein from a top view the capacitor electrode covers at least three sides of the first active area and the gate electrode covers no more than two sides of the second active area; and
forming an input terminal and an output terminal to the capacitor electrode or to the base region, wherein:
the input terminal and the output terminal are spaced apart from each other and are connected to different components within the electronic device;
a resistor-capacitor low-pass filter includes the base region, the capacitor dielectric layer, and the capacitor electrode; and
a transistor structure includes the gate dielectric layer and the gate electrode.
2. The process of claim 1 , further comprising forming a terminal to the base region, wherein the terminal is operable to be biased to a substantially constant voltage.
3. The process of claim 2 , further comprising forming a well region within a substrate, wherein the base region includes the well region.
4. The process of claim 2 , wherein forming the capacitor electrode and forming the gate electrode comprise:
forming a first layer over the capacitor dielectric layer and the gate dielectric layer, wherein the first layer includes a doped semiconductor material;
forming an insulating layer over the first layer;
patterning the first layer and the insulating layer to form a first remaining portion over the capacitor dielectric layer and a second remaining portion over the gate dielectric layer;
removing the insulating layer from over the second remaining portion of the first layer; and
forming a silicide region over the second remaining portion of the first layer, wherein:
the gate electrode includes the silicide region and the second remaining portion of the first layer;
the capacitor electrode includes the first remaining portion of the first layer; and
during forming the silicide region, the first remaining portion of the insulating layer overlies the first remaining portion of the first layer.
5. The process of claim 1 , wherein forming the capacitor electrode comprises:
depositing a layer of semiconductor material; and
annealing the layer to affect grains within the layer.
6. The process of claim 5 , wherein the layer includes a substantially undoped semiconductor material.
7. A process of forming an electronic device comprising:
forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material;
forming a gate dielectric layer over a substrate,
forming a capacitor electrode over the capacitor dielectric layer;
forming a gate electrode over the gate dielectric layer; and
forming an input terminal and an output terminal to the capacitor electrode or to the base region, wherein:
the input terminal and the output terminal are spaced apart from each other and are connected to different components within the electronic device;
a filter includes the base region, the capacitor dielectric layer, and the capacitor electrode; and
a transistor structure includes the gate dielectric layer and the gate electrode,
wherein forming the gate electrode and forming the capacitor electrode comprises:
depositing a layer of semiconductor material;
selectively doping a portion of the layer; and
patterning the layer to form the gate electrode and the capacitor electrode, wherein:
the gate electrode includes a dopant from doping substantially all of the layer and selectively doping the portion of the layer; and
the capacitor electrode does not include a dopant from selectively doping the portion of the layer.
8. The process of claim 1 , wherein forming the capacitor dielectric layer and forming the gate dielectric layer are performed substantially simultaneously during a point in time, include substantially a same composition, and have substantially a same thickness.
9. A process of forming an electronic device comprising:
forming a first capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material;
forming a second capacitor dielectric layer over the base region;
forming a first gate dielectric layer over a substrate;
forming a first capacitor electrode over the first capacitor dielectric layer;
forming a second capacitor electrode over the second capacitor dielectric layer;
forming a first gate electrode over the first gate dielectric layer;
forming first source/drain regions adjacent to the first gate electrode;
forming a field isolation region to define a first active area and a second active area, wherein from a top view the first or second capacitor electrode covers at least three sides of the first active area, and the first gate electrode covers no more than two sides of the second active area;
forming a first input terminal and a first output terminal of a differential resistor-capacitor circuit to the first capacitor electrode, wherein the first input terminal and the first output terminal are spaced apart from each other and are connected to different components within the electronic device; and
forming a second input terminal and a second output terminal of the differential resistor-capacitor circuit to the second capacitor electrode,
wherein:
the differential resistor-capacitor low-pass circuit includes the base region, the first capacitor dielectric layer, the first capacitor electrode, the second capacitor dielectric layer, and the second capacitor electrode; and
a first transistor structure includes the first gate dielectric layer, the first gate electrode, and the first source/drain regions.
10. The process of claim 9 , further comprising:
forming a second gate dielectric layer over the substrate;
forming a second gate electrode over the second gate dielectric layer;
forming second source/drain regions adjacent to the second gate electrode,
wherein:
a second transistor structure includes the second gate dielectric layer, the second gate electrode, and the second source/drain regions.
11. The process of claim 10 , wherein forming the first capacitor dielectric layer, the second capacitor dielectric layer, the first gate dielectric layer, and the second gate dielectric layer are performed substantially simultaneously during a point in time, include substantially a same composition, and have substantially a same thickness.
12. The process of claim 11 , wherein forming the first capacitor electrode, the second capacitor electrode, the first gate electrode, and the second gate electrode comprises:
depositing a first layer over the first capacitor dielectric layer, second capacitor dielectric layer, the first gate dielectric layer, and the second gate dielectric layer; and
patterning the first layer to produce shapes corresponding to the first capacitor electrode, the second capacitor electrode, the first gate electrode, and the second gate electrode.
13. The process of claim 12 , wherein forming the first input terminal and the first output terminal and forming the second input terminal and the second output terminal are performed substantially simultaneously during a point in time.
14. The process of claim 12 further comprising forming a doped region within the base region, wherein forming the first source/drain regions or forming the second source/drain regions is performed substantially simultaneously during a point in time as forming the doped region within the base region.
15. The process of claim 9 , further comprising forming a field isolation region to define a first active region and a second active region, wherein:
forming the first capacitor electrode is performed such that substantially all of the first capacitor electrode overlies the first active region; and
forming the second capacitor electrode is performed such that substantially all of the second capacitor electrode overlies the second active region.
16. The process of claim 9 , further comprising forming a reference terminal that is electrically connected to the filter.
17. The process of claim 10 , wherein the first transistor structure includes an n-channel transistor, and the second transistor structure includes a p-channel transistor.
18. The process of claim 1 , further comprising forming a reference terminal that is electrically connected to the filter.