Method and system of data processor design by sensitizing logical difference
View Patent ↗A method of optimizing a design is disclosed, wherein a target element contributing to an undesirable characteristic in an original netlist is modified to create a modified netlist. A set of test vectors identifying differences between the original netlist and the modified netlist is identified and used to identify a set of corrections. In one disclosed embodiment, the set of corrections is identified by using an error correction algorithm. Each correction of the set of corrections, when applied to the modified netlist, results in a corrected netlist logically the same as the original netlist. One of the corrections is selected that improves the error characteristic of the original netlist. A final equivalency verification is performed as necessary.
1. A method comprising:
modifying an element in a first design representation to create a second design representation, wherein the first design representation represents a first circuit having a first logic function and the second design representation represents a second circuit having a second logic function different than the first logic function;
determining a first test vector to sensitize a logical difference between the first design representation and the second design representation; and
determining a set of corrections based on the first test vector, wherein a correction within the set of corrections identifies a modified design representation logically the same as the first circuit for the first test vector.
2. The method of claim 1 , wherein determining the first test vector includes the logical difference being observable at a primary output of the first circuit and the second circuit.
3. The method of claim 1 further comprising:
applying a first correction from the set of corrections to the second design representation to form a third design representation.
4. The method of claim 1 , wherein modifying the element includes one of removing the element or replacing the element with one or more different elements.
5. The method of claim 4 , wherein the element is associated with a portion of the first design representation having an undesirable design characteristic.
6. The method of claim 5 , wherein the undesirable design characteristic is a propagation delay.
7. The method of claim 5 , wherein the undesirable design characteristic is a race condition.
8. The method of claim 5 , wherein the undesirable design characteristic is power consumption.
9. The method of claim 5 , wherein the undesirable design characteristic is noise consumption.
10. The method of claim 5 , wherein the undesirable design characteristic is low testability.
11. The method of claim 10 , further comprising:
creating a third design representation having a multiplexing device, wherein a first input of the multiplexing device is to receive data based on at least a portion of the first logic function, and the second input of the multiplexing function is to receive data based on at least a portion of the second logic function; and
wherein determining the first test vector includes performing a stuck-at analysis of a select line of the multiplexing device.
12. The method of claim 1 , wherein determining the first test vector includes using an automatic test program generator (ATPG) based program.
13. The method of claim 1 , wherein:
determining a first test vector includes determining a plurality of test vectors to sensitize a logical difference between the first design representation and the second design representation, and
determining the set of corrections includes determining a non-redundant correction based on the plurality of test vectors.
14. A method comprising:
determining a first test vector to sensitize a functionality difference between a first portion of a first design representation and a second portion of the first design representation; and
determining a design representation modification based upon the first test vector, wherein the design representation modification is to be used in a device instead of the first portion and the second portion to provide a desired logical functionality.
15. The method of claim 14 , wherein the desired logical functionality is the same as a logical functionality for the first portion.
16. The method of claim 14 , wherein the design representation modification is different than the first portion of the design representation and the second portion of the design representation.
17. The method of claim 14 , wherein determining the first test vector includes the first test vector sensitizing the functionality difference at a primary output of a device.
18. A system comprising:
a differential test vector generator having a first input to access a first design representation, a second input to access a second design representation, and an output to provide a test vector that sensitizes a logical difference between at least a portion of the first design representation and at least a portion of the second design representation; and
a error correction module having a first input coupled to access the first design representation, a second input coupled to access the second design representation, a third input coupled to the output of the differential test vector generator, and an output to provide a third design representation that is logically equivalent to the first design representation based on the test vector.
19. The system of claim 18 further comprising:
a system verifier having a first input to receive the first design representation and a second input to receive the second design representation, and an output to provide an indication that the first design is functionally equivalent.
20. The system of claim 19 , wherein the system verifier performs a formal verification.
21. The system of claim 20 , wherein the system verifier includes one of an automatic test program generator portion, a binary decision diagram portion, and satisfaction (SAT) solver.
22. A system comprising:
a processing module; and
memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to:
access a design representation having a first portion and a second portion;
determine a test vector to sensitize a logical difference between the first portion and a second portion; and
determine a design representation modification based upon the test vector, wherein the design representation modification is to provide a desired functionality in place of the first portion and the second portion.
23. The system of claim 22 , wherein the operational instructions that determine the test vector includes the test vector sensitizing the logical difference in an observable manner at primary outputs of the design representation.
24. A computer readable medium for storing a data processing routine comprising:
determining a test vector to sensitize a functionality difference between a first portion of a first design representation and a second portion of the first design representation; and
determining a design representation modification based upon the test vector, wherein the design representation modification is to replace the first portion and the second portion to provide a desired logical functionality.
25. The computer readable medium of claim 24 , wherein determining the test vector includes the test vector sensitizing the functionality difference in an observable manner at primary outputs of the first design representation.
26. A method comprising:
coupling a first node to a first data input of a first multiplexing circuit, wherein the functionality of the first node is based upon a first circuit;
coupling a second node to a second data input of the first multiplexing circuit, wherein the functionality of the second node is based upon a second circuit; and
performing a stuck-at analysis at a select input of the first multiplexing circuit to determine logical equivalency of the first circuit and the second circuit.
27. The method of claim 26 , wherein performing the stuck-at analysis includes using an automatic test program generator to perform the stuck-at analysis at the select input.
28. The method of claim 26 further comprising:
coupling a third node to a first data input of a second multiplexing circuit, wherein the functionality of the third node is based upon a third circuit;
coupling a fourth node to a second data input of a second multiplexing circuit, wherein the functionality of the fourth node is based upon a fourth circuit; and
coupling a select node to the select input of the first multiplexing circuit and to a select input of the second multiplexing circuit.
29. The method of claim 28 , wherein the first circuit and third circuit are part of a first device and the second circuit and fourth circuit are part of a second device.
30. The method of claim 28 , wherein the first node and third node are primary outputs of the first device and the second node and third node are primary outputs of the second device.
31. The method of claim 26 , wherein the first node and the second node provide data internal to the first device.
32. A method comprising:
coupling a first node to a first data input of a first multiplexing circuit, wherein the functionality of the first node is based upon a first circuit;
coupling a second node to a second data input of the first multiplexing circuit, wherein the functionality of the second node is based upon a second circuit; and
performing a stuck-at analysis at the select input of the first multiplexing circuit to determine a set of test vectors to sensitize logical differences between the first circuit and the second circuit.
33. The method of claim 32 , wherein performing the stuck-at analysis includes using an automatic test program generator to perform the stuck-at analysis at the select input.
34. The method of claim 32 , wherein the first circuit and second circuit are part of a common device.
35. The method of claim 33 , wherein the logical differences are observable at primary outputs of the common device.