Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods
View Patent ↗A method of generating a layout of one or more planar double gate transistors can include generating a single gate transistor layout at least in part from one or more double gate transistor circuits, logic diagrams, or any combination thereof, and generating the planar double gate transistor layout at least in part from the single gate transistor layout. The method is highly flexible regarding the generation and adjusting of gate shapes and gate contact shapes to ensure the proper connection of the gates to voltage or signal lines, and when such generation, adjusting, or any combination thereof is performed. In one embodiment, a data processing system can include a program that has code in the form of instructions to carry out the method.
1. A method of generating a layout of an electronic device comprising:
generating a first single gate transistor shape at least in part from a double gate transistor circuit schematic, logic diagram, or any combination thereof;
generating the layout including a first planar double gate transistor shape at least in part from the first single gate transistor shape, wherein:
generating the layout further comprises generating a first gate shape, a second gate shape and an active shape for the first planar double gate transistor shape; and
generating the layout is performed such that one of the first and second gate shapes underlies the active shape, and the other of the first and second gate shapes overlies the active shape; and
storing the layout of the electronic device in memory.
2. The method of claim 1 , further comprising adjusting the first gate shape, the second gate shape, or any combination thereof
3. The method of claim 2 , further comprising generating a gate contact indicator associated with the first single gate transistor shape, wherein adjusting the first gate shape, the second gate shape, or both is performed in response to the gate contact indicator.
4. The method of claim 1 , wherein generating the layout further comprises:
generating a first gate contact shape associated with the first gate shape; and
generating a second gate contact shape associated with the second gate shape.
5. The method of claim 4 , further comprising generating a gate contact indicator associated with the first single gate transistor shape, wherein generating the first gate contact shape, generating the second gate contact shape, or both is performed in response to the gate contact indicator.
6. The method of claim 1 , further comprises generating a second single gate transistor shape at least in part from the double gate transistor circuit schematic, logic diagram, or any combination thereof wherein generating the layout further comprises generating a second planar double gate transistor shape at least in part from the second single gate transistor shape.
7. The method of claim 6 , wherein generating the layout further comprises generating a first gate shape and a second gate shape for the second planar double gate transistor shape, wherein:
the first planar double gate transistor shape has a first gate shape and a second gate shape that are not to be electrically connected to each other; and
the second planar double gate transistor shape has a first gate shape and a second gate shape that are to be electrically connected to each other.
8. The method of claim 7 , wherein generating the layout further comprises adjusting the first gate shape, the second gate shape, or both for the second planar double gate transistor shape.
9. The method of claim 6 , wherein generating the layout further comprises generating a first gate contact shape associated with the first gate shape of the second planar double gate transistor shape.
10. The method of claim 9 , wherein generating the layout further comprises replacing the first gate contact shape of the second planar double gate transistor shape with a thru-gate contact shape associated with the first and second gate shapes of the second planar double gate transistor.
11. The method of claim 10 , wherein a separate gate contact shape is not generated for the second gate shape of the second planar double gate transistor shape.
12. The method of claim 10 , wherein generating the layout further comprises:
generating a first gate contact shape to the first gate shape of the first planar double gate transistor shape; and
generating a second gate contact shape to the second gate shape of the first planar double gate transistor shape.
13. The method of claim 6 , further comprising generating the first single gate transistor shape and generating the second single gate transistor shape further comprises:
generating s circuit schematic including a first single gate transistor and a second single gate transistor at least in part from the double gate transistor circuit schematic, logic diagram, or any combination thereof;
generating the first single gate transistor shape at least in part from the circuit schematic; and
generating the second single gate transistor shape at least in part from the circuit schematic.
14. The method of claim 1 , further comprising fabricating the electronic device at least in part using the first planar double gate transistor shape.
15. A method of generating a layout for an electronic device comprising:
generating a circuit schematic including a first single gate transistor and a second single gate transistor at least in part from a double gate transistor circuit schematic, logic diagram, or any combination thereof;
generating a gate contact indicator associated with the first single gate transistor, the second single gate transistor, or any combination thereof;
generating a first single gate transistor shape and a second single gate transistor shape at least in part from the circuit schematic;
generating a layout including a first planar double gate transistor shape and a second planar double gate transistor shape at least in part from the first single gate transistor shape and the second single gate transistor shape, respectively, wherein each of the first planar double gate transistor shape and the second planar double gate transistor shape includes a first gate shape and a second gate shape; and
adjusting the first gate shape of the first planar double gate transistor shape, the second gate shape of the first planar double gate transistor shape, the first gate shape of the second planar double gate transistor shape, the second gate shape of the second planar double gate transistor shape, or any combination thereof; and
storing the first gate shape of the planar double gate transistor shape, the second gate shape of the first planar double gate transistor shape, the first gate shape of the second double gate transistor shape, or any combination thereof in a memory, wherein storing is performed after adjusting the first gate shape of the first planar double gate transistor shape, the second gate shape of the first planar double gate transistor shape, the first gate shape of the second planar double gate transistor shape, the second gate shape of the second planar double gate transistor shape, or any combination thereof.
16. The method of claim 15 , wherein adjusting the first gate shape of the first planar double gate transistor shape, the second gate shape of the first planar double gate transistor shape, the first gate shape of the second planar double gate transistor shape, the second gate shape of the second planar double gate transistor shape, or any combination thereof is performed in response to the gate contact indicator.
17. The method of claim 15 , wherein generating the layout further comprises:
generating first gate contact shapes for the first gate shapes; and
in response to the gate contact indicator:
replacing the first gate contact shape of the second planar double gate transistor shape with a thin-gate contact shape;
generating a second gate contact shape associated with second gate shape of the first planar double gate transistor shape; or
any combination thereof.
18. A memory having code stored therein, wherein a processor is operable to execute the code the code comprising:
an instruction to generate a single gate transistor shape at least in part from a double gate transistor circuit schematic, logic diagram, or any combination thereof;
an instruction to generate the layout including a planar double gate transistor shape at least in pail from the single gate transistor shape;
an instruction to generate a gate contact indicator associated with the single gate transistor; and
an instruction to adjust a first gate shape. a second gate shape, or any combination thereof of the planar double gate transistor layout in response to the gate contact indicator.
19. The memory of claim 18 , wherein:
the an instruction to generate the layout comprises an instruction to generate a first gate shape and a second gate shape of the planar double gate transistor shape; and
the code further comprises:
an instruction to generate a first gate contact indicator associated with the single gate transistor;
an instruction to generate a first gate contact shape associated with the first gate shape; and
an instruction to be executed in response to the gate contact indicator; wherein the instruction includes:
an instruction to replace the first gate contact shape with a thin-gate contact shape associated with the first and second gate shapes; or
an instruction to generate a second gate contact shape associated with second gate shape.