Semiconductor device having a gate with a thin conductive layer
View Patent ↗A semiconductor device ( 10 ) having a gate ( 16, 18 or 16, 18, 26, 28 ) with a thin conductive layer ( 18 ) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics ( 16 ) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer ( 18 ), quantum confinement of carriers within conductive layer ( 18 ) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device ( 10 ) can be reduced. Additional conductive layers (e.g. 28 ) may be used to provide more carriers.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer is characterized as a gate dielectric;
a first conductive layer on the first dielectric layer, wherein the first conductive layer has a thickness of at most approximately 4 nanometers;
a second dielectric layer on the first conductive layer;
a second conductive layer on the second dielectric layer; and
a conductive contact electrically coupled to the first conductive layer and the second conductive layer.
2. The semiconductor device of claim 1 , further comprising a channel region under the gate dielectric, wherein the second dielectric layer on the first conductive layer extends along a length of the channel region.
3. The semiconductor device of claim 1 , wherein the thickness of the first conductive layer is at most approximately 3 nanometers.
4. The semiconductor device of claim 1 , wherein the thickness of the first conductive layer is at most approximately 2 nanometers.
5. The semiconductor device of claim 1 , wherein the second conductive layer is electrically coupled to the first conductive layer.
6. The semiconductor device of claim 5 , further comprising:
a third dielectric layer over the second conductive layer.
7. The semiconductor device of claim 6 , wherein the third dielectric is characterized as an interlayer dielectric (ILD) layer.
8. The semiconductor device of claim 1 , wherein the first conductive layer comprises a metal.
9. A semiconductor device, comprising:
a semiconductor substrate;
a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer is characterized as a gate dielectric;
a first conductive layer on the first dielectric layer, wherein the first conductive layer has
a thickness of at most approximately 4 nanometers;
a second dielectric layer on the first conductive layer;
a second conductive layer in direct contact with the second dielectric layer and electrically coupled to the first conductive layer; and
a conductive contact electrically coupled to the first conductive layer and the second conductive layer.
10. The semiconductor device of claim 9 , further comprising:
a third dielectric layer over the second conductive layer.
11. The semiconductor device of claim 10 , wherein the third dielectric layer is characterized as an ILD layer.
12. The semiconductor device of claim 9 , further comprising a channel region under the gate dielectric, wherein the second dielectric layer on the first conductive layer extends along a length of the channel region.
13. The semiconductor device of claim 9 , wherein the thickness of the first conductive layer is at most approximately 3 nanometers.
14. The semiconductor device of claim 9 , wherein the thickness of the first conductive layer is at most approximately 2 nanometers.
15. The semiconductor device of claim 9 , wherein the first conductive layer comprises a first metal and the second conductive layer comprises a second metal.
16. The semiconductor device of claim 15 , wherein the first metal and the second metal are a same metal.
17. A semiconductor device, comprising:
a semiconductor substrate;
a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer is characterized as a gate dielectric, and wherein an interface between the first dielectric layer and the semiconductor substrate defines an interfacial plane;
a first conductive layer on the first dielectric layer, wherein the first conductive layer forms a quantization filter for carriers in a direction that is normal to the interfacial plane;
a second dielectric layer on the first conductive layer;
a second conductive layer on the second dielectric layer; and
a conductive contact electrically coupled to the first conductive layer and the second conductive layer.
18. The semiconductor device of claim 17 , further comprising a channel region under the gate dielectric, wherein the second dielectric layer on the first conductive layer extends along a length of the channel region.
19. The semiconductor device of claim 17 , wherein the thickness of the first conductive layer is at most approximately 4 nanometers.
20. The semiconductor device of claim 17 , wherein the thickness of the first conductive layer is at most approximately 3 nanometers.
21. The semiconductor device of claim 17 , wherein the thickness of the first conductive layer is at most approximately 2 nanometers.
22. The semiconductor device of claim 17 , wherein the first conductive layer comprises a metal.
23. The semiconductor device of claim 18 , further comprising:
a third dielectric layer over the second conductive layer.
24. The semiconductor device of claim 23 , wherein the third dielectric layer is characterized as an ILD layer.
25. The semiconductor of claim 18 , wherein the second conductive layer comprises a metal.