System and method for reducing power consumption in a low-density parity-check (LDPC) decoder
View Patent ↗A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.
1. A system for reducing power consumption in a Low Density Parity Check (LDPC) decoder, wherein the LDPC decoder comprises a plurality of Bit Node Memory Units (BNMUs) corresponding to a plurality of bit nodes, a plurality of Check Node Memory Units (CNMUs) corresponding to a plurality of check nodes, and a plurality of Check Node and Bit Node Update Units (CNBNUs), each BNMU having at least one bit node from the plurality of bit nodes for storing a bit node message value corresponding to one of the check nodes, each CNMU having at least one check node from the plurality of check nodes for storing check node message values corresponding to one or more bit nodes, each CNBNU associated with a check node and being used for updating the check node and one or more bit nodes corresponding to the check node in one or more iterations of an exchange of messages between the check node and the one or more bit nodes, the system comprising:
a sleep mode checking module that checks whether a check node is in a sleep mode, wherein the check node is in the sleep mode when an absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value; and
a gating circuit, connected to the sleep mode checking module, that turns OFF a CNBNU associated with the check node when the check node is in the sleep mode, wherein turning OFF the CNBNU stops the exchange of messages between the check node and the corresponding one or more bit nodes.
2. The system for reducing power consumption in the LDPC decoder of claim 1 , wherein the sleep mode checking module comprises:
a comparator that compares the absolute value of the message from each of the one or more bit nodes to the threshold value.
3. The system for reducing power consumption in the LDPC decoder of claim 1 , wherein the sleep mode checking module comprises:
a look-up table (LUT) that stores one or more threshold values;
an iteration counter that counts the number of iterations of exchange of messages between a check node and the corresponding one or more bit nodes;
a threshold select unit connected to the look-up table and the iteration counter, wherein the threshold select unit selects a threshold value from the one or more threshold values stored in the LUT based on the number of iterations of the exchange of messages; and
a comparator connected to the threshold select unit that compares the absolute value of the message going to each of the one or more bit nodes to the threshold value.
4. The system for reducing power consumption in the LDPC decoder of claim 1 , wherein the absolute value of the message from each of the one or more bit nodes is a symbol probability.
5. The system for reducing power consumption in the LDPC decoder of claim 1 , wherein the gating circuit comprises:
a memory that stores a status of each check node of the plurality of check nodes, wherein the status includes first information on whether each check node is in a sleep mode;
a controller connected to the memory, wherein the controller provides the status of a check node to the memory based on an input from the sleep mode checking module and generates an enable signal corresponding to the check node based on the status of the check node stored in the memory;
a control register connected to the controller, which stores second information about each check node, wherein the second information includes identification of one or more bit nodes corresponding to each check node; and
a clock gating circuit connected to the controller, wherein the clock gating circuit turns OFF a CNBNU associated with the check node based on the enable signal when the check node is in the sleep mode.
6. A method for reducing power consumption in a Low Density Parity Check (LDPC) decoder, wherein the LDPC decoder comprises a plurality of Bit Node Memory Units (BNMUs) corresponding to a plurality of bit nodes, a plurality of Check Node Memory Units (CNMUs) corresponding to a plurality of check nodes, and a plurality of Check Node and Bit Node Update Units (CNBNUs), each BNMU having at least one bit node from the plurality of bit nodes, wherein each of the at least one bit nodes is used for storing a bit node message value corresponding to one of the check nodes, each CNMU having at least one check node from the plurality of check nodes, wherein each of the at least one check nodes is used for storing check node message values corresponding to one or more of the bit nodes, each CNBNU associated with a check node and being used for updating the check node and one or more bit nodes corresponding to the check node in one or more iterations of an exchange of messages between the check node and the one or more bit nodes, the method comprising the steps of:
selecting a check node for updating, wherein updating the check node comprises modifying the check node message value corresponding to the check node and the bit node message value corresponding to each of the one or more bit nodes corresponding to the check node;
checking whether the check node is in a sleep mode, wherein the check node is in the sleep mode when an absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value; and
turning OFF a CNBNU associated with the check node when the check node is in the sleep mode, wherein turning OFF the CNBNU stops the exchange of messages between the check node and the corresponding one or more bit nodes.
7. The method for reducing power consumption in a LDPC decoder of claim 6 , wherein the step of selecting a check node for updating is performed iteratively for each of the plurality of check nodes.
8. The method for reducing power consumption in a LDPC decoder of claim 6 , wherein the absolute value of the message from going to each of the one or more bit nodes is a symbol probability.
9. The method for reducing power consumption in a LDPC decoder of claim 6 , wherein the step of checking whether the check node is in the sleep mode comprises the steps of:
counting the number of iterations of the exchange of messages between the check node and the one or more bit nodes;
selecting a threshold value from one or more predetermined threshold values based on the number of iterations; and
comparing the absolute value of the message going to each of the one or more bit nodes to the selected threshold value.
10. The method for reducing power consumption in a LDPC decoder of claim 9 , further comprising the step of:
storing a status of the check node, wherein the status includes information on whether the check node is in the sleep mode.
11. The method for reducing power consumption in a LDPC decoder of claim 6 , wherein the step of turning OFF a CNBNU associated with the check node comprises the steps of:
generating an enable signal corresponding to the check node based on the status of the check node; and
turning OFF the CNBNU associated with the check node based on the enable signal.
12. A Low Density Parity Check (LDPC) decoder, comprising:
a plurality of Bit Node Memory Units (BNMUs) corresponding to a plurality of bit nodes, each BNMU having at least one bit node from the plurality of bit nodes;
a plurality of Check Node Memory Units (CNMUs) corresponding to a plurality of check nodes, each CNMU having at least one check node from the plurality of check nodes, wherein each of the at least one check nodes stores a check node message value corresponding to one or more of the bit nodes, and wherein each of the at least one bit nodes stores a bit node message value corresponding to a check node;
a plurality of Check Node and Bit Node Update Units (CNBNUs), wherein each CNBNU updates a check node and one or more of the bit nodes corresponding to said check node in one or more iterations of an exchange of messages between check node and the one or more bit nodes;
a sleep mode checking module that checks whether a check node is in a sleep mode, wherein the check node is in the sleep mode when an absolute value of a message going to each of one or more bit nodes corresponding to the check node is greater than a threshold value; and
a gating circuit that gates turns OFF a CNBNU associated with the check node when the check node is in the sleep mode, wherein turning OFF the CNBNU stops the exchange of messages between the check node and the one or more bit nodes.
13. The LDPC decoder of claim 12 , wherein the sleep mode checking module comprises:
a comparator that compares the absolute value of the message from each of the one or more bit nodes to the threshold value.
14. The LDPC decoder of claim 12 , wherein the sleep mode checking module comprises:
a look-up table (LUT) that stores one or more threshold values;
an iteration counter that counts the number of iterations of the exchange of messages between a check node and the corresponding one or more bit nodes;
a threshold select unit connected to the look-up table and the iteration counter, wherein the threshold select unit selects a threshold value from the one or more threshold values stored in the LUT based on the number of iterations of the exchange of messages; and
a comparator connected to the threshold select unit that compares the absolute value of the parameter of each of the one or more bit nodes to the threshold value.
15. The LDPC decoder of claim 12 , wherein the message from each of the one or more bit nodes is a symbol probability.
16. The LDPC decoder of claim 12 , wherein the gating circuit comprises:
a memory that stores a status of each check node of the plurality of check nodes, wherein the status includes first information on whether the check node is in a sleep mode;
a controller, connected to the memory, wherein the controller provides the status of a check node to the memory based on an input from the sleep mode checking module and generates an enable signal corresponding to the check node based on the status of the check node stored in the memory;
a control register, connected to the controller, wherein the control register stores second information about each check node, wherein the second information includes identification of one or more bit nodes exchanging messages with the check node; and
a clock gating circuit, connected to the controller, which turns OFF a CNBNU associated with the check node based on the enable signal when the check node is in the sleep mode.
17. The LDPC decoder of claim 16 , wherein the enable signal is generated when the check node is in the sleep mode.