Granted Patent B2

US 7,663,470 · App. 11/403,395 · Granted Feb 16, 2010

Abstract

Claims (10)

1. A trimming circuit for generating an adjusting resistance, comprising:

a base resistance circuit;

a first unit, connected to the base resistance circuit, including a first transistor and first and second series connected resistors, wherein the first transistor is connected in parallel with the first and second resistors;

a second unit, connected to the first unit, including a second transistor and a third resistor, wherein the third resistor is connected in parallel to the second transistor; and

a third unit, connected to the second unit, including a third transistor, a series connection section connected in series with the third transistor, and a parallel connection section connected in parallel with the series connection section and the third transistor.

2. The trimming circuit of claim 1 , wherein the first and second resistors each have a resistance R and wherein when the first transistor is off, the resistance of the first unit is 2R and when the first transistor is on, the resistance of the first unit is about zero.

3. The trimming circuit of claim 2 , wherein the third resistor has a resistance R, and wherein when the second transistor is off, the resistance of the second unit is R and when the second transistor is on, the resistance of the second unit is about zero.

4. The trimming circuit of claim 3 , wherein the trimming circuit includes six units having respective predetermined resistances of 2R, R, R/2, R/4, R/8 and R/16.

5. The trimming circuit of claim 1 , wherein the third transistor is an NMOS transistor.

6. The trimming circuit of claim 1 , wherein the base resistance circuit converts an output current to a reference voltage.

Assignments (30)