Memory row/column replacement in an integrated circuit
View Patent ↗An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array ( 50 ) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry ( 92 ). A selected one of these vectors stored in the actual solution storage circuitry ( 92 ) is then used to determine rows and columns in memory array ( 20 ) to be replaced with redundant rows ( 22, 24 ) and redundant columns ( 26 ).
1. A method of replacing memory cells in a memory, the method comprising:
generating a first; plurality of values;
selecting a second plurality of values from the first plurality of values, the second plurality of values representing potential solutions for memory row/column replacement;
determining locations of failed memory cells within a memory array;
using the second plurality of values to store in a first storage circuit, row/column indications of the location of the determined failed memory cells, wherein the memory array is implemented in an integrated circuit, the integratcd circuit includes at least one redundant row of a first number (RR) and at least one redundant column of a second number (RC), wherein the selecting of the second plurality of values from the first plurality of values further includes determined whether each value of the first plurality of values includes one of a number of logical 1's or a number of logical 0's equal to one of RR or RC.
2. The method of claim 1 wherein the generating of the first plurality of values is performed by circuitry of the integrated circuit.
3. The method of claim 1 wherein the selecting is performed by circuitry of the integrated circuit.
4. The method of claim 1 further comprising:
storing the second plurality of values in a second storage circuit.
5. The method of claim 4 wherein a number of values of the second plurality of values stored in the second storage circuit is given by (RR+RC)!/(RR!*RC!).
6. The method of claim 5 wherein the indications are stored in the first storage circuit in a configuration having a first dimension given by (RR+RC)!/(RR!*RC!).
7. The method of claim 5 wherein each value of the second plurality stored in the second storage circuit has a number of bits given by (RC+RR).
8. The method of claim 7 wherein the indications are stored in the first storage circuit in a configuration having a second dimension given by (RC+RR).
9. The method of claim 4 wherein the using of the second plurality of values to store in a the first storage circuit, row/column indications of the location of the determined failed memory cells further includes storing one of a row address or a column address of a failed memory cell at a given location in the first storage circuit depending upon whether a bit of a value of the second plurality corresponding to the given location indicates a row or a column.
10. The method of claim 1 wherein the generating of a first plurality of values further includes operating a counter to provide die first plurality of values.
11. The method of claim 1 wherein die using of the second plurality of values to store in the first storage circuit, row/column indications of the location of the determined failed memory cells further includes using the second plurality of values to determine whether row information or column information of a failed memory cell is stored in the first storage circuit.
12. The method of claim 1 wherein the using of the second plurality of values to store in the first storage circuit, row/column indications of the location of the determined failed memory cells further includes using the second plurality of values to determine whether row information or column information of a failed memory cell is stored within a given location in the first storage circuit.
13. The method of claim 1 further comprising:
if a failed memory cell is determined, using the indications to determine at least one row of a memory array to be replaced by at least one redundant row and/or at least one column of the memory array to be replaced by at least one redundant column.
14. The method of claim 1 further comprising:
if a failed memory cell is determined, replacing at least one row and/or at least one column of the memory array with at least one redundant row and/or at least one redundant column as per a vector selected from the first storage circuit.
15. The method of claim 1 further comprising: manufacturing the integrated circuit.
16. An integrated circuit comprising:
a memory array;
at least one redundant row of a first number (RR) for the memory array;
at least one redundant column of a second number (RC) for the memory array;
a value generation circuit, the value generation circuit including an output to provide a plurality of values;
a selection circuit, the selection circuit including an output to provide selected values of the plurality of values, wherein the selected values represent potential solutions for memory row/column replacement;
a first storage circuit for storing the selected values,
wherein the selection circuitry determines whether a value of the plurality has one of a number of logical 1's or a number of logical 0's equal to one of RR or RC.
17. The integrated circuit of claim 16 wherein the value generation circuit includes a counter.
18. The integrated circuit of claim 16 wherein each of the selected values stored in the first storage circuit has a number of bits given by RC+RR.
19. The integrated circuit of claim 16 wherein a number of selected values stored in the first storage circuit is given by (RR+RC)!/(RR!*RC!).
20. The integrated circuit of claim 19 wherein each of the selected values stored in the first storage circuit has a number of bits given by RC+RR.
21. The integrated circuit of claim 16 further comprising:
a second storage circuit, the second storage circuit for storing indications of rows and columns of memory cell failures of the memory array.
22. The integrated circuit of claim 21 wherein the indications are stored in the second storage circuit in a configuration having a first dimension given by (RR+RC)!/(RR!*RC!).
23. The integrated circuit of claim 22 wherein the indications are stored in the second storage circuit in a configuration having a second dimension given by (RC+RR).
24. The integrated circuit of claim 21 further comprising:
circuitry, having an input coupled to the second storage circuit and an output, the output providing a vector in the second storage circuit;
replacement circuitry, the replacement circuitry for replacing at least one row of the memory array and/or at least one column of the memory array with at least one redundant row and/or at least one redundant column.
25. An integrated circuit comprising;
a memory array;
at least one redundant row for the memory array;
at least one redundant column for the memory array;
means for generating a first plurality of values;
means for selecting a second plurality of values from the first plurality of values, wherein the second plurality at values represent potential solutions for memory row/column replacement, wherein the at least one redundant row is of a first number (RR) and the at least one redundant column is of a second number (RC), wherein a number of values of the second plurality selected is given by (RR+RC)!/(RR!*RC!).
26. The integrated circuit of claim 25 further comprising:
means far using the second plurality of values to store in a storage circuit, row/column indications of Failed memory cells.
27. The integrated circuit of claim 26 wherein the means for using further includes:
means for storing one of a row address or a column address of a failed memory cell at a given location in the storage circuit depending upon whether a bit of a value of the second plurality corresponding to the given location indicates a row or a column.
28. The integrated circuit of claim 26 wherein the means for using further includes:
means for using the second plurality of values to determine whether row information or column information of a failed memory cell is stored in the storage circuit.
29. The integrated circuit of claim 26 wherein the means for using further includes:
means for using the second plurality of values to determine whether row information or column information of a failed memory cell is stored within a given location in the storage circuit.
30. The integrated circuit of claim 25 farther comprising:
a first storage circuit for storing the second plurality of values.
31. The integrated circuit of claim 25 wherein the means for selecting further includes means for determining whether each value of the first plurality of values includes one of a number of logical 1's or a number of logical 0's equal to one of RR or RC.