Multiprocessor system having a shared main memory accessible by all processor units
View Patent ↗A data processing ( 10 ) includes memory management circuitry ( 14 ) which allows additional control over the physical address ( 83 ) and over the address attributes ( 84 ) which are provided for use by data processing system ( 10 ). One use of this additional control over the physical address ( 83 ) and over the address attributes ( 84 ) is to avoid address translation failure and unintended modification of cache ( 13 ) and memory ( 18 ) system state during debugging.
1. A data processing system, comprising:
first storage circuitry which stores at least one alternate address attribute;
second storage circuitry which stores at least one normal address attribute; and
memory management circuitry which receives a received virtual address and at least one received address attribute and which provides, in response, a physical address and at least one corresponding address attribute, wherein the memory management circuitry selects between the at least one received address attribute, the at least one alternate address attribute, and the at least one normal address attribute to provide as the at least one corresponding address attribute.
2. The data processing system of claim 1 , wherein the memory management circuitry selectively provides the at least one alternate address attribute as the first corresponding address attribute based at least in part on an override control indicator.
3. The data processing system of claim 2 , further comprising third storage circuitry which stores an alternate physical address and fourth storage circuitry which stores a normal physical address, wherein the memory management circuitry selectively provides the alternate physical address in place of the normal physical address as the physical address.
4. The data processing system of claim 3 , wherein the memory management circuitry selectively provides the alternate physical address in place of the normal physical address based at least in part on an alternate address indicator.
5. The data processing system of claim 4 , wherein the memory management circuitry selectively provides the received virtual address as the physical address based at least in part on an address translation indicator.
6. The data processing system of claim 5 , further comprising fifth storage circuitry which stores the override control indicator, the alternate address indicator, and the address translation indicator.
7. The data processing system of claim 6 , wherein the override control indicator comprises the alternate address indicator and the address translation indication.
8. The data processing system of claim 3 , wherein the memory management circuitry further comprises a translation lookaside buffer (TLB), wherein the TLB comprises the third storage circuitry which stores the alternate physical address and the fourth storage circuitry which stores the normal physical address.
9. The data processing system of claim 2 , wherein the memory management circuitry selectively provides the received virtual address as the physical address based at least in part on an address translation indicator.
10. The data processing system of claim 1 , wherein the first storage circuitry stores a plurality of alternate address attributes, the second storage circuitry stores a plurality of normal address attributes, and the memory management circuitry provides the physical address and a plurality of corresponding address attributes, and wherein the memory management circuitry selectively provides the plurality of alternate address attributes in place of the plurality of normal address attributes as the plurality of corresponding address attributes.
11. The data processing system of claim 10 , wherein each of the plurality of alternate address attributes and each of the plurality of normal address attributes are characterized as one of an access attribute or an access permission corresponding to the physical address.
12. The data processing system of claim 1 , further comprising:
debug circuitry, coupled to the memory management circuitry, wherein the debug circuitry comprises the first storage circuitry.
13. The data processing system of claim 12 , wherein the debug circuitry is NEXUS compliant.
14. The data processing system of claim 1 , wherein the at least one alternate address attribute and the at least one normal address attribute is characterized as one of an access attribute or an access permission corresponding to the physical address.
15. A data processing system, comprising:
first storage circuitry which stores an alternate physical address;
second storage circuitry which stores a normal physical address; and
memory management circuitry which receives a virtual address, and in response to receiving the virtual address, said memory management circuitry provides a corresponding physical address that is equal to any one of the virtual address, the alternate physical address, and the normal physical address.
16. The data processing system of claim 15 , wherein the memory management circuitry selectively provides the alternate physical address as the corresponding physical address based at least in part on an alternate address indicator.
17. The data processing system of claim 16 , wherein the memory management circuitry comprises a translation lookaside buffer (TLB) comprising the second storage circuitry which stores the normal physical address.
18. The data processing system of claim 17 , wherein the TLB comprises the first storage circuitry which stores the alternate physical address.
19. The data processing system of claim 18 , wherein the TLB stores at least one alternate address attribute corresponding to the alternate physical address and wherein the memory management circuitry provides the at least one corresponding alternate address attribute when the alternate physical address is provided.
20. The data processing system of claim 17 , further comprising third storage circuitry which stores at least one alternate address attribute, and wherein the TLB stores at least one normal address attribute corresponding to the normal physical address, and wherein the memory management circuitry selectively provides the at least one alternate address attribute in place of the at least one normal address attribute, based at least in part on an override control indicator.
21. The data processing system of claim 20 , wherein the override control indicator includes the alternate address indicator.
22. A method for performing memory management in a data processing system having memory management circuitry, comprising:
selectively configuring the memory management circuitry, wherein the memory management control circuitry stores at least one alternate physical address and at least one normal physical address;
receiving a virtual address; and
in response to receiving the virtual address, providing a corresponding physical address, wherein the alternate physical address is selectively provided in place of the normal physical address as the corresponding physical address, wherein neither the alternate physical address nor the normal physical address is required to be identical to the virtual address.
23. The method of claim 22 , further comprising:
receiving an alternate address indicator, wherein the alternate physical address is selectively provided as the corresponding physical address based at least in part on the alternate address indicator.
24. The method of claim 23 , wherein the memory management circuitry includes a translation lookaside buffer (TLB) which stores the normal physical address in a first portion of the TLB and which stores the alternate physical address in a second portion of the TLB, and wherein one of the first or second portion of the TLB is accessed to provide the corresponding physical address based on the alternate address indicator.
25. The method of claim 23 , wherein selectively configuring the memory management circuitry comprises selectively updating the alternate physical address.
26. The method of claim 22 , wherein the providing the corresponding physical address in response to receiving the virtual address is performed during a debug operation.
27. A data processing system, comprising:
first storage circuitry which stores an alternate physical address;
second storage circuitry which stores at least one alternate address attribute;
third storage circuitry which stores a normal physical address;
fourth storage circuitry which stores at least one normal address attribute;
debug circuitry, wherein the debug circuitry performs NEXUS compliant debug operations; and
memory management circuitry, coupled to the debug circuitry, the first storage circuitry, the second storage circuitry, the third storage circuitry, and the fourth storage circuitry, wherein the memory management circuitry, in response to receiving a virtual address during a NEXUS compliant debug operation, selectively provides the alternate physical address in place of the normal physical address as a corresponding physical address based at least in part on an alternate address indicator and selectively provides the at least one alternate address attribute in place of the at least one normal address attribute as a corresponding address attribute based at least in part on an override control indicator, wherein the override control indicator is based at least in part on the alternate address indicator.
28. The data processing system of claim 27 , wherein the memory management circuitry further comprises a translation lookaside buffer (TLB), wherein the TLB comprises the third storage circuitry which stores the normal physical address and the fourth storage circuitry which stores the at least one normal address attribute.
29. The data processing system of claim 28 , wherein a first portion of the TLB comprises the third storage circuitry which stores the normal physical address and the fourth storage circuitry which stores the at least one normal address attribute, and a second portion of the TLB comprises the first storage circuitry which stores the alternate physical address and the second storage circuitry which stores the at least one alternate address attribute.
30. The data processing system of claim 29 , wherein the alternate address indicator and the override control indicator are a same indicator.
31. The data processing system of claim 28 , wherein the debug circuitry comprises the first storage circuitry and the second storage circuitry.
32. The data processing system of claim 27 , wherein the memory management circuitry selectively provides the virtual address in place of the normal physical address as the corresponding physical address based at least in part on an address translation indicator.
33. The data processing system of claim 32 , wherein the override control indicator is based at least in part on the alternate address indicator and the address translation indicator.
34. The data processing system of claim 33 , wherein each of the alternate address indicator and the address translation indicator are stored within a control register within the debug circuitry.
35. A method for performing memory management in a data processing system having a translation buffer, comprising:
receiving a virtual address;
if a predetermined mode is selected, selectively using the virtual address and a first portion of a translation buffer to perform address translation of the virtual address, and providing a first physical address from the first portion of the translation buffer; and
if the predetermined mode is not selected, selectively using the virtual address and a second portion of the translation buffer to perform address translation of the virtual address, and providing a second physical address from the second portion of the translation buffer,
wherein the first and second portions of the translation buffer are different portions of the translation buffer.
36. A method as in claim 35 , further comprising:
selectively bypassing the translation buffer so that no address translation is performed; and
providing the virtual address as the physical address.
37. A method as in claim 36 , wherein the predetermined mode is a debug mode.
38. A method as in claim 37 , wherein the first portion of the translation buffer is only used to perform address translation when the data processing system is in the debug mode.