Memory with recessed devices
View Patent ↗A memory cell includes devices having associated isolation recesses of differing magnitudes. The effective channel width of a corresponding transistor is substantially equal to a channel top surface width plus twice a sidewall width formed by the isolation recesses. In an SRAM cell, a latch transistor has a larger effective channel width than an associated pass transistor by forming larger recesses, and therefore larger sidewalls in isolation layers surrounding the latch transistor and limiting such recesses for pass transistors. During manufacture of the memory cell, a mask is used to mask an area of the pass transistor while exposing an area of the latch transistor. Accordingly, recesses in an isolation layer around the latch transistor are formed without affecting a corresponding area around the pass transistor.
1. An apparatus comprising a static random access memory cell, the static random access memory cell comprising:
a first device having a first isolation recess amount; and
a second device coupled to the first device, the second device having a second isolation recess amount different from the first isolation recess amount, wherein the first device is a pass transistor, the second device is a latch transistor, and wherein
the pass transistor has a first effective channel width being substantially equal to a top surface width of the channel of the pass transistor; and
the latch transistor has a second effective channel width greater than a top surface width of the channel of the latch transistor.
2. The apparatus of claim 1 further comprising a substrate under the first and second devices, wherein the top surfaces of the channels of the pass and latch transistors are substantially parallel with a principle surface of the substrate.
3. The apparatus of claim 2 wherein the second effective channel width is substantially equal to the top surface width of the channel of the latch transistor plus a first sidewall surface width of the channel of the latch transistor plus a second sidewall surface width of the channel of the latch transistor.
4. The apparatus of claim 3 wherein the sidewall surface widths are measured in a plane which is not substantially parallel with the principle surface of the substrate.
5. The apparatus of claim 1 wherein the second effective channel width is substantially equal to a top surface width of the latch transistor plus twice the second isolation recess amount.
6. An apparatus comprising a memory cell, the memory cell comprising:
a first transistor having a first effective channel width; and
a second transistor coupled to the first transistor, the second transistor having a device area substantially equal to the first transistor, the second transistor having a second effective channel width not substantially equal to the first effective channel width,
wherein the first effective channel width is substantially equal to a top surface width of the channel of the first transistor, and
wherein the second effective channel width is greater than a top surface width of the channel of the second transistor, further wherein the second effective channel width is substantially equal to a channel width of a top surface of the channel plus two times a channel width of a side surface of the channel, the top surface of the channel being proximate to a gate of the second transistor substantially in parallel with a first plane, the side surface being proximate to the gate of the second transistor and being not substantially parallel with the first plane.
7. The apparatus of claim 6 wherein the memory cell is a static random access memory cell, the first device is a pass transistor, and the second device is a latch transistor.
8. The apparatus of claim 6 wherein the second transistor is connected to the first transistor.
9. The apparatus of claim 6 further comprising a memory, the memory comprising:
a word line; and
a bit line, the first transistor having a first current handling electrode coupled to the bit line, a second current handling electrode coupled to a current handling electrode of the second transistor, and a control electrode coupled to the word line.
10. The apparatus of claim 9 wherein the memory cell further comprises a load device, the load device having a first terminal coupled to a first power rail, and a second terminal coupled to the second current handling electrode of the first transistor and the current handling electrode of the second transistor.
11. The apparatus of claim 10 wherein the load device is a PMOS FET and the first and second transistors arc NMOS FETs.
12. The apparatus of claim 10 further comprising an integrated circuit, the integrated circuit comprising the memory.
13. The apparatus of claim 6 further comprising an SRAM, the SRAM comprising a plurality of SRAM cells, each SRAM cell comprising:
a pair of cross-coupled inverters, each cross-coupled inverter including a latch transistor having the second effective channel width; and
a pass transistor having the first effective channel width.
14. The apparatus of claim 6 wherein
the first effective channel width is substantially dependent upon a non-segmented surface of the channel of the pass transistor; and
the second effective channel width is dependent upon a segmented surface of the channel of the latch transistor.
15. A method of making a static random access memory cell including first and second devices at first and second locations, the method comprising:
forming a first device of the memory cell to have a first isolation recess amount associated therewith; and
forming a second device of the memory cell having a second isolation recess amount associated therewith, the second isolation recess amount being different from the first isolation recess amount, wherein the first device is a pass transistor, the second device is a latch transistor, and wherein the pass transistor has a first effective channel width being substantially equal to a top surface width of the channel of the pass transistor; and the latch transistor has a second effective channel width greater than a top surface width of the channel of the latch transistor.
16. The method of claim 15 wherein the first device and the second device are formed using the following shared steps:
providing a substrate;
forming an isolation mask layer over the substrate;
removing portions of the isolation mask layer at locations other than the first and second locations;
removing portions of the substrate selective to the isolation mask layer;
depositing an insulating layer over remaining portions of the isolation mask layer and the substrate; and
planarizing down to the remaining portions of the isolation mask layer.
17. The method of claim 16 wherein the substrate is a semiconductor substrate consisting of one of the group consisting of bulk silicon, germanium, silicon on insulator and germanium on insulator.
18. The method of claim 16 wherein the step of forming the isolation mask layer comprises:
forming an oxide layer over the substrate; and
forming a nitride layer over the oxide layer.
19. The method of claim 16 wherein the step of removing the portions of the isolation mask layer comprises:
depositing a resist layer in a pattern selective to the first and second locations;
etching the isolation mask layer; and
removing the resist layer.
20. The method of claim 16 wherein
the step of removing portions of the substrate includes one of the group consisting of performing a dry etch of the substrate and performing a wet etch of the substrate; and
the step of planarizing includes chemical mechanical polishing.
21. The method of claim 16 wherein the step of forming the second device comprises removing portions of the insulating layer selective to the isolation mask layer at the second location but not at the first location.
22. The method of claim 21 wherein the step of forming the second device comprises:
masking the first location; and
etching the second location with an etch that is selective to silicon and nitride.
23. The method of claim 21 wherein the first device and the second device are formed using the following shared steps:
removing remaining portions of the isolation masking layer;
forming a gate dielectric layer; and
forming a gate electrode layer.
24. An SRAM cell formed according to the method of claim 15 .
25. A method of making a memory cell comprising:
designing a pass transistor of the memory cell to have an effective channel width substantially dependent upon a top surface of a channel of the pass transistor; and
designing a latch transistor of the memory cell to have an effective channel width substantially dependent upon a top surface of the channel of the latch transistor and upon a sidewall surface of the latch transistor.
26. The method of claim 25 further comprising:
designing the larch transistor to have an effective channel width larger than the effective channel width of the pass transistor, but to have a substantially similar top surface channel width as the pass transistor.