Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures
View Patent ↗Semiconductor structures, and methods for fabricating semiconductor structures, comprising high dielectric constant stacked structures are provided. A stacked dielectric structure ( 16 ) in accordance with one exemplary embodiment of the present invention has a first amorphous dielectric layer ( 18 ) comprising Hf X Zr 1-X O 2 , where 0≦X≦1. An amorphous interlayer ( 20 ) overlies the first amorphous dielectric layer. The interlayer has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO 4 . A second amorphous dielectric layer ( 22 ) overlies the interlayer. The second amorphous dielectric layer comprises Hf Y Zr 1-Y O 2 , where 0≦Y≦1. The stacked dielectric structure ( 16 ) has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO 4 .
1. A process for fabricating a transistor, the process comprising:
depositing a first amorphous dielectric layer overlying a substrate, said first amorphous dielectric layer comprising Hf X Zr i-X O 2 , wherein 0≦X≦1;
forming an amorphous interlayer overlying said first amorphous dielectric layer, said amorphous interlayer having a net dielectric constant approximately no less than the dielectric constant of HfZrO 4 , wherein said amorphous interlayer is formed such that a chemical composition at a first surface of said amorphous interlayer is different from a chemical composition at a second surface of said amorphous interlayer;
depositing a second amorphous dielectric layer overlying said amorphous interlayer to form a stacked dielectric structure, said second amorphous dielectric layer comprising HfZr 1-Y O 2 , where 0≦Y≦1, wherein the stacked dielectric structure has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO 4 ;
forming a source region within said substrate; and
forming a drain region within said substrate.
2. The process for fabricating a transistor of claim 1 , the process further comprising:
forming a second amorphous interlayer overlying said second amorphous dielectric layer, said second amorphous interlayer having a net dielectric constant approximately no less than the dielectric constant of HfArO 4 ; and
depositing a third amorphous dielectric layer overlying said second amorphous interlayer, said third amorphous dielectric layer comprising Hf N Zr 1-N O 2 , wherein 0≦N≦1.
3. The process for fabricating a transistor of claim 1 , wherein the step of depositing a first amorphous dielectric layer comprises the step of depositing a first amorphous layer of HfO 2 .
4. The process for fabricating a transistor of claim 1 , wherein the step of forming said first amorphous interlayer comprises the step of depositing a material selected from the group consisting of lanthanum aluminum oxide (La X Al Y O 3 ), lanthanum scandium oxide (La X Sc Y O 3 ), lanthanum lutetium oxide (La XLu Y O 3 ), strontium titanate (Sr X Ti Y O 3 ), barium titanate (Ba X Ti Y O 3 ), strontium barium titanate (Sr X Ba Y Ti Z O 3 ), tantalum oxide (Ta 2 O 5 ), barium zirconium oxide (Ba X Zr Y O 3 ), strontium zirconium oxide (Sr X Zr Y O 3 ), and combinations thereof, wherein X, Y and Z are any numbers greater than zero.
5. The process for fabricating a transistor of claim 1 , wherein the step of forming said first amorphous interlayer comprises:
forming a first sublayer having a first chemical composition; and
forming a second sublayer having a second chemical composition that is different from said first chemical composition.
6. The process for fabricating a transistor of claim 5 , wherein the step of forming said first amorphous interlayer comprises:
forming said first sublayer having a first thickness; and
forming said second sublayer having a second thickness that is different from said first thickness.
7. The process for fabricating a transistor of claim 1 , wherein the step of forming said first amorphous interlayer comprises forming said first amorphous interlayer so that said first amorphous interlayer has a chemical composition at a first surface of said amorphous interlayer that is different from a chemical composition at a second surface.
8. The process for fabricating a transistor of claim 1 , wherein the steps of depositing a first amorphous dielectric layer, forming an amorphous interlayer, and depositing a second amorphous dielectric layer are performed so that the stacked dielectric structure has a thickness in the range of about 1 to about 10 nanometers.
9. A method for modifying a work function of a gate structure of a transistor, the method comprising:
forming a layer of SiO X overlying a silicon substrate, where X is any number greater than zero;
depositing a first amorphous dielectric layer of material comprising Hf Y Zr 1-Y O 2 overlying said layer of SiO X , where 0≦Y≦1;
forming an amorphous interlayer overlying said first amorphous dielectric layer, wherein said amorphous interlayer has a net dielectric constant approximately no less than the dielectric constant of HfArO 4 and wherein said amorphous interlayer has a chemical composition at a first sin-face of said amorphous interlayer that is different from a chemical composition at a second surface of said amorphous interlayer;
depositing a second amorphous dielectric layer of material comprising Hf z Zr 1-Z O 2 overlying said amorphous interlayer, where 0≦Z≦1; and
depositing a metal layer overlying said second amorphous dielectric layer.
10. The method for modifying a work function of a gate structure of a transistor of claim 9 , wherein the step of depositing said first amorphous dielectric layer comprises the step of depositing a first amorphous layer of HfO 2 .
11. The method for modifying a work function of a gate structure of a transistor of claim 9 , wherein the step of forming said amorphous interlayer comprises the step of depositing a material selected from the group consisting of lanthanum aluminum oxide (La X Al Y O 3 ), lanthanum scandium oxide (La X Sc Y O 3 ), lanthanum lutetium oxide (La X Lu Y O 3 ), strontium titanate (Sr X Ti Y O 3 ), barium titanate (Ba X Ti Y O 3 ), strontium barium titanate (Sr X Ba Y Ti Z O 4 barium zirconium oxide (Ba X Zr Y O 3 ), strontium zirconium oxide (Sr X Zr Y O 3 ), and combinations thereof, wherein X, Y and Z are any numbers greater than zero.
12. The method for modifying a work function of a gate structure of a transistor of claim 9 , wherein the step of fanning said amorphous interlayer comprises:
forming a first sublayer having a first chemical composition; and
forming a second sublayer having a second chemical composition that is different from said first chemical composition.
13. The method for modifying a work function of a gate structure of a transistor of claim 12 , wherein the step of forming said amorphous interlayer comprises:
forming said first sublayer having a first thickness; and
forming said second sublayer having a second thickness that is different from said first thickness.