IP Library Granted Patent US 6,908,852
Granted Patent B2
US 6,908,852 · App. 10/353,886 · Granted Jun 21, 2005

Method of forming an arc layer for a semiconductor device

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Quick Facts
Patent No.
US 6,908,852
App. No.
10/353,886
Granted
Jun 21, 2005
Kind
B2
Abstract

An antireflective coating (ARC) layer for use in the manufacture of a semiconductor device. The ARC layer has a bottom portion that has a lower percentage of silicon than a portion of the ARC layer located above it. The ARC layer is formed on a metal layer, wherein the lower percentage of silicon of the ARC layer inhibits the unwanted formation of suicides at the metal layer/ARC layer interface. In some embodiments, the top portion of the ARC layer has a lower percentage of silicon than the middle portion of the ARC layer, wherein the lower percentage of silicon at the top portion may inhibit the poisoning of a photo resist layer on the ARC layer. In one embodiment, the percentage of silicon can be increased or decreased by decreasing or increasing the ratio of the flow rate of a nitrogen containing gas with respect to the flow rate of a silicon containing gas during a deposition process.

Claims (86)

1. A method of making a semiconductor device, comprising:

forming a metal layer over a semiconductor substrate; and

depositing an antireflective coating (ARC) layer over the metal layer by a method comprising:

mixing a nitrogen-containing gas with a silicon-containing gas over the metal layer at a first ratio of nitrogen to silicon;

after mixing at the first ratio, mixing the nitrogen-containing gas and the silicon-containing gas over the metal layer at a second ratio of nitrogen to silicon, wherein the first ratio is greater than the second ratio; and

after mixing at the second ratio, mixing the nitrogen-containing gas and the silicon-containing gas over the metal layer at a third ratio of nitrogen to silicon, wherein the third ratio is greater than the second ratio.

2. The method of claim 1 , wherein forming the ARC layer further comprises:

after mixing at the first ratio and before mixing at the second ratio, mixing the nitrogen-containing gas and the silicon-containing gas over the metal layer at a fourth ratio of nitrogen to silicon, wherein the fourth ratio is less than the first ratio and greater than the second ratio; and

after mixing at the second ratio and before mixing at the third ratio, mixing the nitrogen-containing gas and the silicon-containing gas over the metal layer at a fifth ratio of nitrogen to silicon, wherein the fifth ratio is less than the third ratio and greater than the second ratio.

3. The method of claim 1 , wherein mixing the nitrogen-containing gas and the silicon-containing gas forms silicon nitride over the metal layer.

4. The method of claim 3 , wherein mixing the nitrogen-containing gas and the silicon-containing gas at the first ratio forms silicon nitride with a nitrogen concentration of at least the nitrogen concentration of stoichiometric silicon nitride.

5. The method of claim 1 , wherein the silicon-containing gas comprises silane.

6. The method of claim 1 , wherein the nitrogen-containing gas comprises ammonia.

7. The method of claim 1 , wherein the silicon-containing gas comprises a gas selected from silane, disilane, and dichlorosilane, trisilane, trichlorosilane, and silicon tetrafluoride.

8. The method of claim 1 , wherein the nitrogen-containing gas comprises a gas selected from ammonia, nitrogen, nitrogen oxide, and nitrous oxide.

9. The method of claim 1 wherein the ARC layer is deposited on the metal layer.

10. The method of claim 1 further comprising:

depositing a layer of photo resist over the ARC layer;

patterning the layer of photo resist to form a pattern in the layer of photo resist.

11. The method of claim 10 further comprising:

etching the ARC layer and the metal layer according to the pattern to leave a gate stack of a transistor; and

forming a source and a drain of the transistor.

12. The method of claim 10 wherein the layer of photo resist is deposited on the ARC layer.

13. The method of claim 1 wherein the metal layer is formed on a dielectric layer.

14. A method of forming a semiconductor device, comprising:

forming a metal layer over a semiconductor substrate;

depositing an antireflective coating (ARC) layer over the metal layer by a method comprising:

forming a first portion of the ARC layer having a first ratio of silicon to silicon reactants, wherein the silicon reactants consist of at least one of oxygen and nitrogen;

after forming the first portion, forming a second portion of the ARC layer having a second ratio of silicon to silicon reactants, wherein the second ratio is greater than the first ratio; and

after forming the second portion, forming a third portion of the ARC layer having a third ratio of silicon to silicon reactants, wherein the second ratio is greater than the third ratio.

15. The method of claim 14 further comprising:

depositing a layer of photo resist over the ARC layer;

patterning the layer of photo resist to form a pattern in the layer of photo resist.

16. The method of claim 15 further comprising:

etching the ARC layer and the metal layer according to the pattern to leave a gate stack of a transistor; and

forming a source and a drain of the transistor.

17. The method of claim 15 wherein the layer of photo resist is deposited on the ARC layer.

18. The method or claim 14 , wherein the forming the ARC layer further comprises:

after forming the first portion and before forming the second portion, forming a fourth portion of the ARC layer having a fourth ratio of silicon to silicon reactants, wherein the fourth ratio is greater than the first ratio and less than the second ratio; and

after forming the second portion and before forming the third portion, forming a fifth portion of the ARC layer having a fifth ratio of silicon to silicon reactants, wherein the fifth ratio is greater than the third ratio and less than the second ratio.

19. The method of claim 14 , wherein the ARC layer comprises silicon nitride.

20. The method of claim 14 , wherein the ARC layer comprises material selected from silicon nitride, silicon oxynitride, metal silicon nitride, and metal silicon oxynitride.

21. The method of claim 14 wherein the ARC layer is deposited on the metal layer.

22. The method of claim 14 wherein the metal layer is formed on a dielectric layer.

23. A method of making a semiconductor device, comprising:

forming a metal layer over a semiconductor substrate;

depositing an antireflective coating (ARC) layer over the metal layer by a method comprising:

forming a first portion of the ARC layer having a first percentage of silicon;

after forming the first portion, forming a second portion of the ARC layer having a second percentage of silicon, wherein the second percentage of silicon is greater than the first percentage of silicon; and

after forming the second portion, forming a third portion of the ARC layer having a third percentage of Silicon, wherein the second percentage is greater than the third percentage.

24. The method of claim 23 wherein the ARC layer is deposited on the metal layer.

25. The method of claim 23 further comprising:

depositing a layer of photo resist over the ARC layer;

patterning the layer of photo resist to form a pattern in the layer of photo resist.

26. The method of claim 25 further comprising:

etching the ARC layer and the metal layer according to the pattern to leave a gate stack of a transistor; and

forming a source and a drain of the transistor.

27. The method of claim 25 wherein the layer of photo resist is deposited on the ARC layer.

28. The method of claim 23 wherein the metal layer is formed on a dielectric layer.

29. The method of claim 23 , wherein the forming the ARC layer further comprises:

after forming the first portion and before forming the second portion, forming a fourth portion of the ARC layer having a fourth percentage of silicon, wherein the fourth percentage is greater than the first percentage and less than the second percentage; and

after forming the second portion and before forming the third portion, forming a fifth portion of the ARC layer having a fifth percentage of silicon, wherein the fifth percentage is greater than the third percentage and less than the second percentage.

30. A method of making a semiconductor device, comprising:

forming a metal layer over a semiconductor substrate;

depositing an antireflective coating (ARC) layer over the metal layer by a method comprising:

mixing a nitrogen-containing gas with a silicon-containing gas over the metal layer at a first ratio of nitrogen to silicon; and

after mixing at the first ratio, mixing the nitrogen-containing gas and the silicon-containing gas over the metal layer at a second ratio of nitrogen to silicon, wherein the first ratio is greater than the second ratio; and

forming a metal gate of a transistor from the metal layer;

wherein depositing the ARC layer further comprises:

after mixing at the second ratio, mixing the nitrogen-containing gas and the silicon-containing gas over the metal layer at a third ratio of nitrogen to silicon, wherein the third ratio is greater than the second ratio.

31. A method of forming a semiconductor device, comprising:

forming a metal layer over a semiconductor substrate;

depositing an antireflective coating (ARC) layer over the metal layer by a method comprising:

forming a first portion of the ARC layer having a first ratio of silicon to silicon reactants, wherein the silicon reactants consist of at least one of oxygen and nitrogen; and

after forming the first portion, forming a second portion of the ARC layer having a second ratio of silicon to silicon reactants, wherein the second ratio is greater than the first ratio; and

forming a metal gate of a transistor from the metal layer;

wherein the depositing the ARC layer further comprises:

after forming the second portion, forming a third portion of the ARC layer having a third ratio of silicon to silicon reactants, wherein the second ratio is greater than the third ratio.

32. A method of making a semiconductor device, comprising:

forming a metal layer over a semiconductor substrate;

depositing an antireflective coating (ARC) layer over the metal layer by a method comprising:

forming a first portion of the ARC layer having a first percentage of silicon; and

after forming the first portion, forming a second portion of the ARC layer having a second percentage of silicon, wherein the second percentage of silicon is greater than the first percentage of silicon; and

forming a metal gate of a transistor from the metal layer;

wherein depositing the ARC layer further comprises;

after forming the second portion, forming a third portion of the ARC layer having a third percentage of silicon, wherein the second percentage is greater than the third percentage.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →