Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing
View Patent ↗A semiconductor fabrication process includes forming a gate electrode overlying a substrate. A first silicon nitride spacer is formed adjacent the gate electrode sidewalls and a disposable silicon nitride spacer is then formed adjacent the offset spacer. An elevated source/drain structure, defined by the boundaries of the disposable spacer, is then formed epitaxially. The disposable spacer is then removed to expose the substrate proximal to the gate electrode and a shallow implant, such as a halo or extension implant, is introduced into the exposed substrate proximal the gate electrode. A replacement spacer is formed substantially where the disposable spacer existed a source/drain implant is done to introduce a source/drain impurity distribution into the elevated source drain. The gate electrode may include an overlying silicon nitride capping layer and the first silicon nitride spacer may contact the capping layer to surround the polysilicon gate electrode in silicon nitride.
1. A semiconductor fabrication process comprising:
forming a gate electrode overlying a substrate;
forming an oxide liner on sidewalls of the gate electrode;
forming an offset spacer of silicon nitride adjacent the oxide liner;
forming an intermediate liner of silicon oxide adjacent the offset spacer;
forming a disposable spacer of silicon nitride adjacent the intermediate liner;
forming an elevated source/drain overlying the substrate and displaced laterally from sidewalls of the gate electrode by the disposable spacer;
following forming the elevated source/drain removing the intermediate oxide liner and the disposable spacer to expose the upper surface of the substrate and implanting halo and extension implants into the exposed substrate;
following performing the halo and extension implants, forming a replacement intermediate oxide liner and a replacement spacer located substantially where the original intermediate oxide liner and disposable spacer were located; and
forming an antireflective coating (ARC) of silicon nitride overlying the gate electrode.
2. The process of claim 1 , wherein the offset spacer contacts the ARC to enclose the gate electrode in silicon nitride.
3. A semiconductor fabrication process comprising:
forming a gate electrode overlying a substrate;
forming an oxide liner on sidewalls of the gate electrode;
forming an offset spacer of silicon nitride adjacent the oxide liner;
forming an intermediate liner of silicon oxide adjacent the offset spacer;
forming a disposable spacer of silicon nitride adjacent the intermediate liner;
forming an elevated source/drain overlying the substrate and displaced laterally from sidewalls of the gate electrode by the disposable spacer;
following forming the elevated source/drain removing the intermediate oxide liner and the disposable spacer to expose the upper surface of the substrate and implanting halo and extension implants into the exposed substrate; and
following performing the halo and extension implants, forming a replacement intermediate oxide liner and a replacement spacer located substantially where the original intermediate oxide liner and disposable spacer were located.
4. The process of claim 3 , wherein forming the gate electrode includes forming a silicon nitride capping layer overlying a polysilicon gate electrode.
5. The process of claim 4 , wherein the first silicon nitride spacer contacts the capping layer to surround the polysilicon gate electrode in silicon nitride.
6. The process of claim 3 , wherein the first silicon nitride spacer is formed from a silicon nitride film having a thickness of approximately 150 Angstroms.
7. The process of claim 6 , wherein the disposable silicon nitride spacer is formed from a silicon nitride film having a thickness of approximately 900 Angstroms.
8. The process of claim 3 , further comprising rapid thermally annealing the wafer following formation of the disposable spacer by exposing the wafer to an ambient maintained at a temperature of approximately 1060° C. for a duration of approximately 5 seconds.
9. The process of claim 3 , further comprising depositing cobalt over the wafer following the source/drain implant and heating the wafer to react the cobalt where it contacts silicon including silicon in the elevated source/drain and silicon in the gate electrode.
10. The process of claim 3 , further comprising, following formation of the replacement spacer, performing a source/drain implant to introduce a source/drain impurity distribution into the elevated source/drain.
11. The process of claim 3 , wherein forming the elevated source/drain includes epitaxial formation of the elevated source/drain at a temperature of at least 1000° C.
12. A semiconductor fabrication process, comprising:
forming a gate electrode overlying a substrate;
forming an oxide liner on sidewalls of the gate electrode;
forming a silicon nitride offset spacer adjacent the oxide liner;
forming an intermediate liner of silicon oxide adjacent the offset spacer;
forming a disposable silicon nitride spacer adjacent the offset spacer;
forming an elevated source/drain structure overlying regions of the substrate not protected by the gate electrode or the disposable spacer;
without removing the offset spacer, removing the disposable spacer and the intermediate oxide liner to expose the substrate proximal to the gate electrode;
implanting an impurity distribution into the exposed substrate proximal the gate electrode;
forming a replacement intermediate oxide liner and a replacement spacer substantially where the intermediate liner and the disposable spacer existed; and
after forming the replacement spacer, performing a source/drain implant to introduce a source/drain impurity distribution into the elevated source drain.