Method and system for incorporating via redundancy in timing analysis
View Patent ↗A method of conducting timing analysis on an integrated circuit design includes performing a first routing operation on the design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database, and performing a second routing operation on the synthesized design to generate a second routed design that does not include redundant vias, and storing the second routed design in a second design database. Then, extractions are performed on the first and second designs and delay calculations are performing on the first and second extractions files. The first and second delay calculations are compared to determine a delay difference between the first and second designs and timing analysis is performed using the delay difference.
1. A method of conducting timing analysis on an integrated circuit design, comprising:
performing physical synthesis on the integrated circuit design;
performing a first routing operation on the synthesized design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database;
performing a second routing operation on the synthesized design to generate a second routed design that does not include redundant vias, and storing the second routed design in a second design database;
performing extractions on the first and second designs using the first and second design databases to generate first and second extraction files using a system for performing timing analysis;
performing first and second delay calculations on the first and second extractions files;
comparing the first and second delay calculations to determine a delay difference between the first and second designs; and
performing timing analysis using the delay difference.
2. The method of conducting timing analysis according to claim 1 , further comprising:
ascertaining that results of the timing analysis do not meet a timing requirement;
performing a further routing operation on the second routed design to generate a third routed design and storing the third routed design in a third database;
performing extraction on the third routed design using the third database to generate a third extraction file;
performing delay calculations on the third extraction file;
comparing the first and third delay calculations to determine a new delay difference between the first and third designs; and
performing timing analysis using the new delay difference.
3. The method of conducting timing analysis of claim 1 , wherein performing the timing analysis further includes incorporating the delay difference into the second extraction file.
4. The method of conducting timing analysis of claim 1 , wherein the first delay calculation generates a first minimum delay and the second delay calculation generates a second minimum delay, and a delay difference thereof is used for a hold timing check.
5. The method of conducting timing analysis of claim 1 , wherein the first delay calculation generates a first maximum delay and the second delay calculation generates a second maximum delay, and a delay difference thereof is used for a setup timing check.
6. The method of conducting timing analysis of claim 1 , wherein the step of performing timing analysis includes performing a static timing analysis, electromigration analysis, and signal integrity check.
7. The method of conducting timing analysis of claim 1 , further comprising the steps of:
performing GDS integration on the first design using the first design database to generate a GDS file; and
performing chip level static timing analysis on the GDS file.
8. The method of conducting timing analysis of claim 7 , further comprising the step of performing design rules checks using the GDS file.
9. The method of conducting timing analysis of claim 8 , further comprising the step of performing a rule-based tiling operation on the GDS file.
10. The method of conducting timing analysis of claim 1 , wherein the first routing operation generates the first routed design and the first routed design includes redundant vias and fat vias.
11. A system for conducting timing analysis on an integrated circuit design, comprising:
a router for routing the integrated circuit design wherein the router generates a first routed design that includes redundant vias and a second routed design that does not include redundant vias;
an extraction module for extracting parasitics from the first and second routed designs;
a delay calculation module for calculating a plurality of first delay values and a plurality of second delay values respectively for each of the first and second designs;
a delay difference calculation module for comparing the first and second delay values and generating a plurality of delay differences therefrom; and
a timing analysis module for performing a timing analysis on the first design using the plurality of delay differences.
12. The system for conducting timing analysis on an integrated circuit design of claim 11 , wherein the plurality of first delay values and the plurality of second delay values each include a minimum delay and a maximum delay for a timing stage in each of the first and second designs.
13. The system for conducting timing analysis on an integrated circuit design of claim 12 , wherein the plurality of delay differences includes a maximum delay difference, which is obtained from a difference between a maximum delay from the plurality of first delay values and a maximum delay from the plurality of second delay values.
14. The system for conducting timing analysis on an integrated circuit design of claim 13 , wherein the maximum delay difference is incorporated into the maximum delay from the plurality of second delay values before performing the timing analysis for a setup check.
15. The system for conducting timing analysis on an integrated circuit design of claim 12 , wherein the plurality of delay differences includes a minimum delay difference, which is obtained from a difference between a minimum delay from the plurality of first delay values and a minimum delay from the plurality of second delay values.
16. The system for conducting timing analysis on an integrated circuit design of claim 15 , wherein the minimum delay difference is incorporated into the minimum delay from the plurality of second delay values before performing the timing analysis for a hold check.