Multi-gate enhancement mode RF switch and bias arrangement
View Patent ↗Methods and apparatus are provided for RF switches ( 100, 200 ). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors ( 50, 112, 114 ). When used in pairs ( 112, 114 ) each has its source ( 74, 133 ) coupled to a first common RF I/O port ( 116 ) and drains coupled respectively to second and third RF I/O ports ( 118, 120 ), and gates ( 136, 138 ), coupled respectively to first and second control terminals ( 122, 124 ). The multi-gate regions ( 66, 68 ) of the FETs ( 50 ) are parallel coupled, spaced-apart and serially arranged between source ( 72 ) and drain ( 76 ). Lightly doped n-regions (Ldd, Lds) are provided serially arranged between the spaced-apart multi-gate regions ( 66, 68 ), the lightly doped n-regions (Ldd, Lds) being separated by more heavily doped n-regions ( 84 ). Bias resistances ( 132, 134 ) are provided between the sources ( 72, 133 ) and control terminals ( 122, 124 ) so as to provide a DC path between the control terminals ( 122, 124 ) that maintains the source ( 72, 133 ) voltage at the proper bias potential for enhancement mode operation.
1. An n-channel enhancement mode field effect transistor (FET) radio frequency (RF) switch, comprising:
a first source;
a second source coupled to the first source;
a first RF input/output (I/O) port coupled to the first and second sources;
a first drain;
a second drain;
a second RF input/output (I/O) port coupled to the first drain;
a third RF I/O port coupled to the second drain;
multiple parallel coupled first gate regions serially arranged and spaced apart between the first source and first drain;
multiple parallel coupled second gate regions serially arranged and spaced apart between the second source and the second drain;
first and second lightly doped n-regions, wherein each first gate region is separated from each other first gate region by the first and second lightly doped n-regions;
a first more heavily doped n-region as compared with the first and second lightly doped n-regions, which is located between the first gate regions, separating the first and second lightly doped n-regions;
third and fourth lightly doped n-regions, wherein each second gate region is separated from each other second gate region by the third and fourth lightly doped n-regions; and
a second more heavily doped n-region as compared with the third and fourth lightly doped n-regions, which is located between the second gate regions, separating the third and fourth lightly doped n-regions.
2. The RF switch of claim 1 , further comprising:
first bias resistance Rb coupled between the first source and a first node coupled to the multiple parallel coupled first gate regions; and
second bias resistances Rb′ coupled between the second source and a second node coupled to the multiple parallel coupled second gate regions.
3. The RF switch of claim 2 further comprising:
a first control input port coupled to the first node;
a second control input port coupled to the second node;
wherein the first node is coupled to each of the multiple parallel coupled first gate regions by a gate resistance Rg′; and
wherein the second node is coupled to each of the multiple parallel coupled second gate regions by a gate resistance Rg′.
4. The RF switch of claim 3 wherein Rb˜Rb′ and Rg˜Rg′ and a bias voltage between the multiple parallel coupled first gate regions and the first source is determined at least in part by the relationship [Rb+Rg]/[Rb+NRg] wherein N is one less than a total number of RF I/O ports.
5. The RF switch of claim 4 further comprising:
a DC blocking capacitor coupled between the first RF I/O port and the first and second sources;
a second DC blocking capacitor coupled between the second RF I/O port and the first drain; and
a third DC blocking capacitor coupled between the third RF I/O port and the second drain.
6. The RF switch of claim 1 wherein the first source, the first drain, and the multiple parallel coupled first gate regions form a first transistor, and the second source, the second drain, and the multiple parallel coupled second gate regions form a second transistor, and the first and second transistors are formed substantially simultaneously on a common substrate.
7. An n-channel enhancement mode field effect transistor (FET) radio frequency (RF) switch, comprising:
a first source;
a first drain;
a first gate region;
a second gate region;
a third gate region, wherein the first gate region, the second gate region, and the third gate region are parallel coupled, serially arranged, and spaced apart between the first source and first drain;
first lightly doped n-regions on a first side of the first gate region, the second gate region, and the third gate region;
second lightly doped n-regions on a second opposite side of the first gate region, the second gate region, and the third gate region, wherein the first gate region is separated from the second gate region by a first lightly doped n-region and a second lightly doped n-region, and the second gate region is separated from the third gate region by another first lightly doped n-region and another second lightly doped n-region;
a first more heavily doped n-region as compared with the first and second lightly doped n-regions, which is located between the first gate region and the second gate region, and is directly adjacent to both the first lightly doped n-region and the second lightly doped n-region; and
a second more heavily doped n-region as compared with the first and second lightly doped n-regions, which is located between the second gate region and the third gate region, and is directly adjacent to both the another first lightly doped n-region and the another second lightly doped n-region.
8. The RF switch of claim 7 , further comprising:
a second source coupled to the first source;
a first RF input/output (I/O) port coupled to the first and second sources;
a second drain;
a second RF I/O port coupled to the first drain;
a third RF I/O port coupled to the second drain; and
fourth, fifth, and sixth parallel coupled gate regions serially arranged and spaced apart between the second source and the second drain.
9. The RF switch of claim 8 , further comprising:
first bias resistance Rb coupled between the first source and a first node coupled to the first, second, and third gate regions; and
second bias resistances Rb′ coupled between the second source and a second node coupled to the fourth, fifth, and sixth gate regions.
10. The RF switch of claim 9 further comprising:
a first control input port coupled to the first node;
a second control input port coupled to the second node;
wherein the first node is coupled to each of the first, second, and third gate regions by a gate resistance Rg; and
wherein the second node is coupled to each of the fourth, fifth, and sixth gate regions by a gate resistance Rg′.
11. The RF switch of claim 10 wherein Rb˜Rb′ and Rg˜Rg′ and a bias voltage between the first, second, and third gate regions and the first source is determined at least in part by the relationship [Rb+Rg]/[Rb+NRg] wherein N is one less than a total number of RF I/O ports.
12. The RF switch of claim 11 further comprising:
a DC blocking capacitor coupled between the first RF I/O port and the first and second sources;
a second DC blocking capacitor coupled between the second RF I/O port and the first drain; and
a third DC blocking capacitor coupled between the third RF I/O port and the second drain.
13. An n-channel enhancement mode field effect transistor (FET) radio frequency (RF) switch, comprising:
a first source;
a first drain;
a first gate region;
a second gate region, wherein the first gate region and the second gate region are parallel coupled, serially arranged, and spaced apart between the first source and first drain;
first lightly doped n-regions on a first side of the first gate region and the second gate region;
second lightly doped n-regions on a second opposite side of the first gate region and the second gate region, wherein the first gate region is separated from the second gate region by a first lightly doped n-region and a second lightly doped n-region;
a first more heavily doped n-region as compared with the first and second lightly doped n-regions, which is located between the first gate region and the second gate region, and is directly adjacent to both the first lightly doped n-region and the second lightly doped n-region;
a second source coupled to the first source;
a first RF input/output (I/O) port coupled to the first and second sources;
a second drain;
a second RF I/O port coupled to the first drain;
a third RF I/O port coupled to the second drain; and
multiple additional gate regions that are parallel coupled, serially arranged, and spaced apart between the second source and the second drain.
14. The RF switch of claim 13 , further comprising:
third and fourth lightly doped n-regions, wherein each of the multiple additional gate regions is separated from each other of the multiple additional gate regions by the third and fourth lightly doped n-regions; and
a second more heavily doped n-region as compared with the third and fourth lightly doped n-regions, which is located between the multiple additional gate regions, separating the third and fourth lightly doped n-regions.
15. The RF switch of claim 14 , further comprising:
first bias resistance Rb coupled between the first source and a first node coupled to the first and second gate regions; and
second bias resistances Rb′ coupled between the second source and a second node coupled to the multiple additional gate regions.
16. The RF switch of claim 15 , further comprising:
a first control input port coupled to the first node;
a second control input port coupled to the second node;
wherein the first node is coupled to each of the first and second gate regions by a gate resistance Rg; and
wherein the second node is coupled to each of the multiple additional gate regions by a gate resistance Rg′.
17. The RF switch of claim 16 , wherein Rb˜Rb′ and Rg˜Rg′ and a bias voltage between the first and second gate regions and the first source is determined at least in part by the relationship [Rb+Rg]/[Rb+NRg] wherein N is one less than a total number of RF I/O ports.
18. The RF switch of claim 17 further comprising:
a DC blocking capacitor coupled between the first RF I/O port and the first and second sources;
a second DC blocking capacitor coupled between the second RF I/O port and the first drain; and
a third DC blocking capacitor coupled between the third RF I/O port and the second drain.
19. The RF switch of claim 13 , wherein the first source, the first drain, the first gate region, and the second gate region form a first transistor, and the second source, the second drain, and the multiple additional gate regions form a second transistor, and the first and second transistors are formed substantially simultaneously on a common substrate.