Method and circuit for maintaining I/O pad characteristics across different I/O supply voltages
View Patent ↗A circuit implements a method to adjust input/output (I/O) characteristics of an I/O pad circuit ( 10 ) depending upon which value of an I/O supply voltage is used within a range of supply voltages. An I/O supply voltage being supplied to the pad circuit is detected by detecting ( 18, 20 ) its value relative to a known reference ( 16 ). Portions of the I/O pad circuit are selectively enabled in response to the detected I/O supply voltage. By selecting the ratio of P-channel and N-channel transistors, physical characteristics of the circuit are controlled. Examples of the controlled physical characteristics include slew rate, signal rise and fall times, and duty cycle control which is controlled by forcing all rising and falling edges to have a midpoint at the same point in time. Therefore a same I/O pad circuit may be optimally used in numerous applications regardless of the supply voltage value.
1. A method for adjusting input/output (I/O) characteristics of an I/O pad circuit having an I/O pad, comprising:
selecting one of a plurality of different I/O supply voltages to power the I/O pad circuit, wherein the different I/O supply voltages comprise two or more of a nominal 1.8 volts, a nominal 2.5 volts, a nominal 3.3 volts, or a nominal 5.0 volts, further wherein the nominal 1.8 volts comprises a range of 1.62–1.98 volts, the nominal 2.5 volts comprises a range of 2.30–2.70 volts, the nominal 3.3 volts comprises a range of 3.0–3.6 volts, and the nominal 5.0 volts comprises a range of 4.5–5.5 volts;
detecting an I/O supply voltage being supplied to the I/O pad circuit by detecting whether a value of the I/O supply voltage is greater than or less than a known reference voltage; and
enabling or disabling portions of the I/O pad circuit in response to the detected I/O supply voltage, wherein enabling or disabling portions of the I/O pad circuit adjusts the I/O characteristics of the I/O pad circuit as a function of the detected I/O supply voltage.
2. The method of claim 1 , further comprising:
dividing the I/O supply voltage into a plurality of divided voltages using one or more voltage dividers and comparing each of the plurality of divided voltages with the known reference voltage; and
using results of the comparing as detection control signals to control the enabling or disabling of the portions of the I/O pad circuit.
3. The method of claim 1 , wherein the I/O characteristics include one or more of output voltage rise and fall time, output voltage slew rate, output signal duty cycle, input signal DC threshold levels, input signal hysteresis, or a prescribed current supplied to the I/O pad.
4. The method of claim 1 , wherein detecting the I/O supply voltage comprises one of
(a) comparing the I/O supply voltage to a reference voltage and outputting a voltage detect signal, the voltage detect signal having a first state indicative that the I/O supply voltage is more than the reference voltage and a second state indicative that the I/O supply voltage is less than the reference voltage, or
(b) comparing the I/O supply voltage to a plurality of reference voltages and outputting corresponding voltage detect signals, the voltage detect signals having a first state indicative that the I/O supply voltage is more than a corresponding reference voltage and a second state indicative that the I/O supply voltage is less than the corresponding reference voltage.
5. The method of claim 1 , wherein detecting the I/O supply voltage comprises one of
(a) inputting the I/O supply voltage to a voltage divider and providing an output of the voltage divider to a first input of a comparator, wherein the voltage divider is configured for outputting a ratio of the I/O supply voltage, and inputting a reference voltage to a second input of the comparator, wherein the comparator outputs a voltage detect signal, the voltage detect signal having a first state indicative that the output of the voltage divider is more than the reference voltage and a second state indicative that the voltage divider output is less than the reference voltage, or
(b) inputting the I/O supply voltage to a plurality of voltage dividers and providing an output of each of the plurality of voltage dividers to a first input of each of a plurality of comparators, and inputting a reference voltage to a second input of each of the plurality of comparators, wherein the plurality of voltage dividers are configured for outputting different ratios of the I/O supply voltage, and wherein each of the plurality of comparators outputs a voltage detect signal, the voltage detect signal of each of the plurality of comparators having a first state indicative that a corresponding voltage divider output is more than the reference voltage and a second state indicative that the corresponding voltage divider output is less than the reference voltage.
6. A method for adjusting input/output (I/O) characteristics of an I/O pad circuit having an I/O pad, control logic and at least one of (i) an output circuit portion, (ii) an input circuit portion, or (iii) an external leakage offset guarantee portion, comprising:
selecting one of a plurality of different I/O supply voltages to power the I/O pad circuit;
detecting an I/O supply voltage being supplied to the I/O pad circuit; and
enabling or disabling portions of the I/O pad circuit in response to the detected I/O supply voltage, wherein enabling or disabling portions of the I/O pad circuit adjusts the I/O characteristics of the I/O pad circuit as a function of the detected I/O supply voltage and further comprises one of:
(a) enabling the output circuit portion while disabling the input circuit portion and the external leakage offset guarantee portion, or
(b) enabling the input circuit portion while disabling the external leakage offset guarantee portion and the output circuit portion, or
(c) enabling the external leakage offset guarantee portion while disabling the input circuit portion and the output circuit portion, or
(d) enabling one or more of the output circuit portion or the external leakage offset guarantee portion while disabling the input circuit portion, or
(e) enabling one or more of the input circuit portion or the external leakage offset guarantee portion while disabling the output circuit portion, or
(f) enabling one or more of the input circuit portion or the output circuit portion while disabling the external leakage offset guarantee portion.
7. The method of claim 6 , further wherein enabling the output circuit portion comprises adjusting an output device size of the output circuit portion as a function of the detected I/O supply voltage, further wherein enabling the input circuit portion comprises adjusting an input device size of the input circuit portion as a function of the detected I/O supply voltage, and further wherein enabling the external leakage offset guarantee portion comprises adjusting a device size of the external leakage offset guarantee portion as a function of the detected I/O supply voltage.
8. The method of claim 7 , still further wherein with respect to the output circuit portion, maintaining one or more of output voltage rise and fall time, output voltage slew rate or output signal duty cycle, still further wherein with respect to the input circuit portion, maintaining one or more of a prescribed hysteresis or a prescribed input threshold, the input threshold including one or more of a low point threshold and a high point threshold, and still further wherein with respect to the external leakage offset guarantee portion, maintaining a prescribed current supplied to the I/O pad.
9. A method for adjusting input/output (I/O) characteristics of an I/O pad circuit across different I/O supply voltages comprising:
detecting an I/O supply voltage being supplied to the I/O pad circuit; and
enabling or disabling portions of the I/O pad circuit in response to the detected I/O supply voltage, wherein the I/O pad circuit includes control logic and one or more of (i) an output circuit portion, (ii) an input circuit portion, or (iii) an external leakage offset guarantee portion, and wherein enabling or disabling portions of the I/O pad circuit adjusts the I/O characteristics of the I/O pad circuit as a function of the detected I/O supply voltage, wherein the I/O characteristics specified at a first I/O supply voltage are substantially maintained at a second I/O supply voltage different from the first I/O supply voltage, the enabling or disabling further comprising one of:
(a) enabling the output circuit portion while disabling the input circuit portion and the external leakage offset guarantee portion, or
(b) enabling the input circuit portion while disabling the external leakage offset guarantee portion and the output circuit portion, or
(c) enabling the external leakage offset guarantee portion while disabling the input circuit portion and the output circuit portion, or
(d) enabling one or more of the output circuit portion or the external leakage offset guarantee portion while disabling the input circuit portion, or
(e) enabling one or more of the input circuit portion or the external leakage offset guarantee portion while disabling the output circuit portion, or
(f) enabling one or more of the input circuit portion or the output circuit portion while disabling the external leakage offset guarantee portion.
10. The method of claim 9 , wherein detecting the I/O supply voltage comprises one of:
(a) comparing the I/O supply voltage to a reference voltage and outputting a voltage detect signal, the voltage detect signal having a first state indicative that the I/O supply voltage is more than the reference voltage and a second state indicative that the I/O supply voltage is less than the reference voltage, or
(b) comparing the I/O supply voltage to a plurality of reference voltages and outputting corresponding voltage detect signals, the voltage detect signals having a first state indicative that the I/O supply voltage is more than a corresponding reference voltage and a second state indicative that the I/O supply voltage is less than the corresponding reference voltage.
11. The method of claim 9 , further wherein enabling the output circuit portion includes adjusting an output device size of the output circuit portion as a function of the detected I/O supply voltage, further wherein enabling the input circuit portion includes adjusting an input device size of the input circuit portion as a function of the detected I/O supply voltage, and further wherein enabling the external leakage offset guarantee portion includes adjusting a device size of the external leakage offset guarantee portion as a function of the detected I/O supply voltage.
12. The method of claim 11 , still further wherein with respect to the output circuit portion, maintaining one or more of output voltage rise and fall time, output voltage slew rate or output signal duty cycle, still further wherein with respect to the input circuit portion, maintaining one or more of a prescribed hysteresis or a prescribed input threshold, the input threshold including one or more of a low point threshold and a high point threshold, and still further wherein with respect to the external leakage offset guarantee portion, maintaining a prescribed current supplied to the I/O pad.
13. An integrated circuit having an I/O pad circuit with an I/O pad configured for adjusting input/output (I/O) characteristics of the I/O pad circuit across different I/O supply voltages comprising:
means for detecting an I/O supply voltage being supplied to the I/O pad circuit; and
means for enabling or disabling portions of the I/O pad circuit in response to the detected I/O supply voltage, wherein the I/O pad circuit includes control logic and one or more of (i) an output circuit portion, (ii) an input circuit portion, or (iii) an external leakage offset guarantee portion, and wherein enabling or disabling portions of the I/O pad circuit adjusts the I/O characteristics of the I/O pad circuit as a function of the detected I/O supply voltage, wherein the I/O characteristics specified at a first I/O supply voltage are substantially maintained at a second I/O supply voltage different from the first I/O supply voltage, said means for enabling or disabling further comprising (a) means for enabling at least one of the output circuit portion and the external leakage offset guarantee portion while disabling the input circuit portion, or (b) means for enabling at least one of the input circuit portion and the external leakage offset guarantee portion while disabling the output circuit portion, or (c) means for enabling at least one of the input circuit portion and the output circuit portion while disabling the external leakage offset guarantee portion.
14. The integrated circuit of claim 13 , wherein said means for detecting the I/O supply voltage comprises a comparator for comparing the I/O supply voltage to a reference voltage and outputting a voltage detect signal, the voltage detect signal having a first state indicative that the I/O supply voltage is more than the reference voltage and a second state indicative that the I/O supply voltage is less than the reference voltage.
15. The integrated circuit of claim 13 , wherein said means for detecting the I/O supply voltage comprises a comparator for comparing the I/O supply voltage to a reference voltage and outputting corresponding voltage detect signals, the voltage detect signals having a first state indicative that the I/O supply voltage is more than a corresponding reference voltage and a second state indicative that the I/O supply voltage is less than the corresponding reference voltage.
16. The integrated circuit of claim 13 , further wherein said means for enabling the output circuit portion comprise means for adjusting an output device size of the output circuit portion as a function of the detected I/O supply voltage, further wherein said means for enabling the input circuit portion comprises means for adjusting an input device size of the input circuit portion as a function of the detected I/O supply voltage, and further wherein said means for enabling the external leakage offset guarantee portion comprises means for adjusting a device size of the external leakage offset guarantee portion as a function of the detected I/O supply voltage.
17. The integrated circuit of claim 16 , still further wherein said means for enabling the output circuit portion maintains one or more of output voltage rise and fall time, output voltage slew rate or output signal duty cycle, still further wherein said means for enabling the input circuit portion maintains one or more of a prescribed hysteresis or a prescribed input threshold, the input threshold comprising one or more of a low point threshold and a high point threshold, and still further wherein said means for enabling the external leakage offset guarantee portion maintains a prescribed current supplied to the I/O pad.