IP Library Granted Patent US 7,241,636
Granted Patent B2
US 7,241,636 · App. 11/033,008 · Granted Jul 10, 2007

Method and apparatus for providing structural support for interconnect pad while allowing signal conductance

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Quick Facts
Patent No.
US 7,241,636
App. No.
11/033,008
Granted
Jul 10, 2007
Kind
B2
Abstract

A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.

Claims (53)

1. A method for providing structural support for an interconnect pad, the method comprising:

providing a substrate;

providing a first metal layer overlying the substrate, the first metal layer having a plurality of openings;

providing a first electrically insulating layer overlying the first metal layer;

providing a second metal layer overlying the first electrically insulating layer, the second metal layer having a plurality of openings;

providing an interconnect pad overlying the second metal layer, the interconnect pad defining an interconnect pad area;

creating a physical layout shape from a logic operation on the first metal layer and the second metal layer;

determining a value X which is a metal density of the physical layout shape within a region of the interconnect pad; and

using the value X to determine if sufficient alignment of the plurality of openings of the first metal layer and the plurality of openings of the second metal layer exist for sufficient structural support.

2. The method of claim 1 , further comprising:

requiring the value X to be less than or equal to a predetermined threshold.

3. The method of claim 2 wherein the predetermined threshold comprises 0.85.

4. The method of claim 2 wherein the predetermined threshold comprises a range from 0.80 to 0.85, inclusive.

5. The method of claim 2 wherein the predetermined threshold comprises a range from 0.70 to 0.95, inclusive.

6. The method of claim 1 , further comprising:

providing a second electrically insulating layer overlying the second metal layer; and

providing a third metal layer interposed between the second electrically insulating layer and the interconnect pad, the third metal layer having a plurality of openings.

7. The method of claim 6 wherein the first electrically insulating layer and the second electrically insulating layer comprise a same material.

8. The method of claim 1 wherein the first electrically insulating layer comprises a dielectric.

9. The method of claim 1 wherein the first electrically insulating layer has a permittivity less than 4.

10. The method of claim 1 , wherein the first electrically insulating layer has a modulus value less than 80 gigaPascals.

11. The method of claim 1 , wherein the plurality of openings in the first metal layer and the plurality of openings in the second metal layer are substantially filled with the first electrically insulating layer.

12. The method of claim 1 , wherein the first metal layer and the second metal layer respectively have a physical metal density in a range of 20-80% for respective areas of the first metal layer and the second metal layer.

13. The method of claim 1 , further comprising:

providing one or more vias through the first electrically insulating layer to electrically connect at least a portion of the first metal layer to at least a portion of the second metal layer.

14. The method of claim 1 , further comprising:

providing a passivation layer interposed between the interconnect pad and the second metal layer.

15. The method of claim 1 wherein at least one device is formed in the substrate underlying the interconnect pad.

16. A method for providing structural support for an interconnect pad, the method comprising:

providing a substrate;

providing a first conductive layer overlying the substrate, the first conductive layer having a plurality of openings;

providing a first electrically insulating layer overlying the first conductive layer;

providing a second conductive layer overlying the first electrically insulating layer, the second conductive layer having a plurality of openings;

providing an interconnect pad overlying the second conductive layer, the interconnect pad defining an interconnect pad area;

creating a physical layout shape from a logic operation on the first conductive layer and the second conductive layer;

determining a value X which is a density of the physical layout shape within a region of the interconnect pad; and

using the value X to determine if sufficient alignment of the plurality of openings of the first conductive layer and the plurality of openings of the second conductive layer exist for sufficient structural support.

17. The method of claim 16 further comprising:

providing a second electrically insulating layer overlying the second conductive layer; and

providing a third conductive layer interposed between the second electrically insulating layer and the interconnect pad, the third conductive layer having a plurality of openings.

18. The method of claim 16 further comprising:

providing one or more vias through the first electrically insulating layer to electrically connect at least a portion of the first conductive layer to at least a portion of the second conductive layer.

19. The method of claim 16 further comprising:

providing a passivation layer interposed between the interconnect pad and the second conductive layer.

20. A method for providing structural support for an interconnect pad, the method comprising:

providing a substrate having one or more active or passive devices formed therein;

providing a first conductive layer overlying the substrate, the first conductive layer having a plurality of openings;

providing a first electrically insulating layer overlying the first conductive layer;

providing a second conductive layer overlying the first electrically insulating layer, the second conductive layer having a plurality of openings;

providing an interconnect pad overlying the second conductive layer, the interconnect pad defining an interconnect pad area;

creating a physical layout shape from a Boolean OR operation on the first conductive layer and the second conductive layer;

determining a value X which is a density of the physical layout shape within a region of the interconnect pad; and

using the value X to determine if sufficient alignment of the plurality of openings of the first conductive layer and the plurality of openings of the second conductive layer exist for sufficient structural support.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →