IP Library Granted Patent US 7,091,712
Granted Patent B2
US 7,091,712 · App. 10/843,805 · Granted Aug 15, 2006

Circuit for performing voltage regulation

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Quick Facts
Patent No.
US 7,091,712
App. No.
10/843,805
Granted
Aug 15, 2006
Kind
B2
Abstract

A circuit ( 10, 100 ) is used to perform voltage regulation. In one embodiment, a voltage regulator ( 11 ) is used in conjunction with an output transistor ( 24 ) to form a circuit ( 10 ) which operates to regulate the voltage drop from a first node ( 30 ) to a second node ( 28 ). This second node ( 28 ) may be used to provide power to circuitry ( 27 ). The areas of several transistors ( 20–25 ) in circuit ( 10 ) may be adjusted so that negative and positive temperature coefficients may be balanced such that the circuit ( 10 ) behaves as desired over a range of voltages and temperatures. Note that in one embodiment, circuit ( 10 ) is a 2-terminal device.

Claims (57)

1. A circuit having a first output terminal, comprising:

a first current source having an input coupled to a power supply terminal, and an output;

a second current source having an input coupled to the power supply terminal, and an output;

a first transistor having a first current electrode and a control electrode coupled to the output of the first current source, and a second current electrode coupled to the first output terminal;

a second transistor having a first current electrode coupled to the output of the second current source, a control electrode coupled to the control electrode of the first transistor, and a second current electrode;

an impedance having a first terminal coupled to the second current electrode of the second transistor and a second terminal coupled to the first output terminal; and

a third transistor having a first current electrode coupled to the power supply terminal, a control electrode coupled to the first current electrode of the second transistor, and a second current electrode coupled to the first output terminal,

wherein the first output terminal is not connected to a negative rail.

2. The circuit of claim 1 , wherein the first, second, and third transistors are MOS transistors.

3. The circuit of claim 2 , wherein the first, second, and third transistors are N channel transistors.

4. The circuit of claim 1 , wherein the first, second, and third transistors are bipolar transistors.

5. The circuit of claim 4 , wherein the bipolar transistors are NPN transistors.

6. The circuit of claim 1 , wherein the first and second current sources are MOS transistors.

7. The circuit of claim 1 , wherein a voltage provided at the first output terminal can be varied significantly when a voltage provided at the power supply terminal is not varied significantly.

8. The circuit of claim 1 , wherein the first and second current sources are further characterized as responding to a reduction in voltage on the first output terminal by supplying more current.

9. The circuit of claim 1 , wherein the impedance comprises an MOS transistor.

10. The circuit of claim 9 , wherein the MOS transistor has a first current electrode as the first terminal coupled to the second current electrode of the second transistor, a second current electrode as the second terminal coupled to the first output terminal, and a gate coupled to a ground terminal.

11. The circuit of claim 1 , further comprising a capacitive element having a first terminal coupled to the control electrode of the third transistor and a second terminal coupled to the first output terminal.

12. The circuit of claim 1 having a second output terminal further comprising:

a third current source having an input coupled to the first output terminal, and an output;

a fourth current source having an input coupled to the first output terminal, and an output;

a fourth transistor having a first current electrode and a control electrode coupled to the output of the third current source, and a second current electrode coupled to the second output terminal;

a fifth transistor having a first current electrode coupled to the output of the fourth current source, a control electrode coupled to the control electrode of the fourth transistor, and a second current electrode;

a second impedance having a first terminal coupled to the second current electrode of the fifth transistor and a second terminal coupled to the second output terminal; and

a sixth transistor having a first current electrode coupled the first output terminal, a control electrode coupled to the first current electrode of the fourth transistor, and a second cuirent electrode coupled to the second output terminal.

13. A circuit having a first output terminal, comprising:

a regulator circuit coupled between a positive power supply terminal and the first output terminal for providing a reference voltage; and

an output transistor having a first current electrode coupled to the positive power supply terminal, a control electrode for receiving the reference voltage, and a second current electrode coupled to the first output terminal;

wherein a voltage of the first output terminal exceeds a negative rail during operation of the circuit.

14. The circuit of claim 13 , wherein the regulator comprises:

a pair of current sources that each provide equal currents.

15. The circuit of claim 14 , wherein all of the current received by the regulator circuit passes to the first output terminal.

16. The circuit of claim 13 , wherein the regulator increases the reference voltage in response to a decrease in voltage at the first output terminal.

17. The circuit of claim 13 , wherein the regulator comprises:

a first current source having an input coupled to a power supply terminal, and an output;

a second current source having an input coupled to the power supply terminal, and an output;

a first transistor having a first current electrode and a control electrode coupled to the output of the first current source, and a second current electrode coupled to the first output terminal;

a second transistor having a first current electrode coupled to the output of the second current source for providing the reference voltage, a control electrode coupled to the control electrode of the first transistor, and a second current electrode; and

an impedance having a first terminal coupled to the second current electrode of the second transistor and a second terminal coupled to the first output terminal.

18. The circuit of claim 13 having a second output terminal, further comprising:

a second regulator circuit coupled between the first output terminal and the second output terminal for providing a second reference voltage; and

a second output transistor having a first current electrode coupled to the first output terminal, a control electrode for receiving the second reference voltage, and a second current electrode coupled to the second output terminal;

wherein all of the current received by the second regulator circuit passes to the second output terminal.

19. A circuit having a first output terminal, comprising:

a current mirror for establishing a reference current for establishing a reference voltage, wherein the reference current increases in response to a decrease in voltage at the output terminal;

an impedance that carries the reference current and that decreases in magnitude with increases in temperature; and

an output transistor for receiving the reference voltage and providing an output current at the output terminals,

wherein the voltage at the output terminal exceeds a negative rail voltage during operation of the circuit.

20. The circuit of claim 19 , wherein the current mirror comprises:

a first current source having an input coupled to a power supply terminal, and an output;

a second current source having an input coupled to the power supply terminal, and an output;

a first transistor having a first current electrode and a control electrode coupled to the output of the first current source, and a second current electrode coupled to the first output terminal; and

a second transistor having a first current electrode coupled to the output of the second current source for providing the reference voltage, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the impedance.

21. The circuit of claim 19 having a second output terminal, further comprising:

a second current mirror for establishing a second reference current for establishing a second reference voltage, wherein the second reference current increases in response to a decrease in voltage at the second output terminal;

a second impedance that carries the second reference current and that decreases in magnitude with increases in temperature; and

a second output transistor for receiving the second reference voltage and providing a second output current at the second output terminal.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
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To: NXP B.V.
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From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
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SECURITY AGREEMENT Recorded May 13, 2010
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To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
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