Method and apparatus for maintaining topographical uniformity of a semiconductor memory array
View Patent ↗A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.
1. A semiconductor device comprising:
an active area formed in a semiconductor substrate;
a plurality of non-volatile memory cells formed in the active area, each of the plurality of non-volatile memory cells having a source, a drain, and a gate stack, the gate stack comprising:
a first oxide layer formed over the active area;
a discrete charge storage layer formed over the first oxide layer;
an second oxide layer formed over the discrete charge storage layer; and
a control gate formed over the second oxide layer; and
a ring formed around the plurality of memory cells, the ring having a composition and height substantially the same as a composition and height of the gate stack.
2. The semiconductor device of claim 1 , wherein the discrete charge storage layer is a floating gate.
3. The semiconductor device of claim 1 , wherein the ring is electrically isolated from the plurality of memory cells.
4. The semiconductor device of claim 1 , wherein the ring is continuous.
5. The semiconductor device of claim 1 , wherein the active area is surrounded by a trench etched into the semiconductor substrate.
6. The semiconductor device of claim 1 , further comprising an active boundary formed around the memory array, wherein the ring is formed directly over the active boundary.
7. The semiconductor device of claim 1 , further comprising a nitride spacer formed on a side of the ring.
8. The semiconductor device of claim 1 , wherein the first oxide comprises a tunnel oxide and the second oxide comprises an oxide-nitride-oxide (ONO) stack.
9. The semiconductor device of claim 1 , wherein the active area comprises a plurality of longitudinal active regions, each of the longitudinal active regions surrounded by trenches.
10. The semiconductor device of claim 1 , further comprising an insulating layer formed over the plurality of memory cells and over the ring, wherein a chemical mechanical polishing process is used to planarize the insulating layer.
11. A semiconductor device comprising:
a memory array having a plurality of non-volatile memory cells, each non-volatile memory cell of the plurality of non-volatile memory cells having a gate stack, the gate stack including a control gate and a discrete charge storage layer; and
a dummy stack ring formed around the memory array, the dummy stack ring having a composition and height substantially the same as a composition and height of the gate stack.
12. The semiconductor device of claim 11 , wherein the dummy stack ring is continuous.
13. The semiconductor device of claim 11 , wherein the plurality of non-volatile memory cells is formed on a plurality of parallel longitudinal active regions, each of the longitudinal active regions surrounded by trenches.
14. The semiconductor device of claim 11 , wherein the discrete charge storage layer comprises a floating gate.
15. The semiconductor device of claim 11 , further comprising an insulating layer formed over the plurality of non-volatile memory cells and over the dummy stack ring, wherein a chemical mechanical polishing process is used to planarize the insulating layer.