Reference circuit
View Patent ↗A reference circuit comprises a first current generator comprising a first transistor operably coupled to a second transistor and having respective base current corresponding to a positive temperature dependence of the reference circuit. A resistance is operably coupled to the first current generator and arranged to provide a second current corresponding to a negative temperature dependence of the reference circuit. A second current generator is operably coupled to the resistance and the first current generator that generates a combined current as a sum of the second current and base current. In this manner, the output voltage of the curvature compensated voltage and/or current reference circuit is substantially linear and substantially independent of the operating temperature of the circuit.
1. A reference circuit arranged to employ curvature compensation comprising:
a first current generator comprising a first transistor operably coupled to a second transistor and having respective base current corresponding to a positive temperature dependence of the reference circuit;
the reference circuit:
a resistance operably coupled to the first current generator and arranged to provide a second current corresponding to a negative temperature dependence of the reference circuit; and
a second current generator operably coupled to the resistance and the first current generator that generates a combined current as a sum of the second current and base current wherein the sum of the base current and second current is input to a curvature compensation network that generates a third current proportional to a non-linear term in the transmitter voltage thereby compensating non-linearity in the output voltage.
2. A reference circuit according to claim 1 wherein a sum of the base current, second current and third current is input to an output resistor thereby converting a current to form a curvature compensated temperature-independent output voltage.
3. A reference circuit according to claim 2 , wherein the sum of the base current, second and third currents is independent of temperature in both a first order manner as well as in a second order manner.
4. A reference circuit according to claim 2 , wherein a current mirror circuit operably coupled to the first current generator and second current generator and arranged to force collector currents of the number of transistors to be substantially equal.
5. A reference circuit according to claim 1 wherein the sum of the base current, second and third currents is independent of temperature in both a first order manner as well as in a second order manner.
6. A reference circuit according to claim 1 wherein a current mirror circuit operably coupled to the first current generator and second current generator and arranged to force collector currents of the number of transistors to be substantially equal.
7. A reference circuit according to claim 1 wherein the current mirror circuit is an BJT or an MOS current mirror.
8. A reference circuit according to claim 1 wherein the temperature independence is derived as:
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9. A reference circuit according to claim 1 wherein the reference circuit is configured to provide second order compensation comprising an additional network having at least two PMOS transistors operably coupled to a diode-connected bipolar transistor and a resistor.
10. A reference circuit according to claim 9 wherein a second current mirror circuit having a third PMOS transistor;
wherein:
a gate terminal of a third PMOS transistor is connected to drain and gate terminals of a second diode-connected PMOS transistor of the first current mirror;
a source of the third PMOS transistor connected to a supply voltage bus; and
a drain of the third PMOS transistor connected to an output node.
11. A reference circuit according to claim 10 wherein the second current mirror circuit having a fourth PMOS transistor wherein a drain and gate of the fourth PMOS transistor are connected to the drain of the first PMOS transistor.
12. A reference circuit according to claim 11 wherein the second current mirror circuit having a fifth PMOS transistor having its gate connected to drain and gate terminals of the fourth PMOS transistor.
13. A reference circuit according to claim 12 wherein sources of the fourth PMOS transistor and fifth PMOS transistor being connected to a supply voltage bus.
14. A reference circuit according to claim 13 , wherein a drain of the fifth PMOS transistor coupled with a drain of a third PMOS transistor at the output node.
15. A reference circuit according to claim 12 wherein a drain of the fifth PMOS transistor coupled with a drain of a third PMOS transistor at the output node.
16. A reference circuit according to claim 15 , wherein:
the reference circuit generates a second temperature-dependent voltage and comprises a sixth PMOS transistor, a seventh PMOS transistor, and an NPN transistor; and
such that the gates of the sixth and seventh PMOS transistors are connected to drain and gate terminals of the second PMOS transistor and a fourth diode-connected PMOS transistor respectively.
17. A reference circuit according to claim 16 wherein a source of the sixth and the seventh PMOS transistors connected to the supply voltage bus.
18. A reference circuit according to claim 17 wherein drains of a sixth PMOS transistor and seventh PMOS transistor being connected to base and collector terminals of an NPN transistor whose emitter is grounded.
19. A reference circuit according to claim 10 , wherein:
the reference circuit generates a second temperature-dependent voltage and comprises a sixth PMOS transistor, a seventh PMOS transistor, and an NPN transistor; and
such that the gates of the sixth and seventh PMOS transistors are connected to drain and gate terminals of the second PMOS transistor and a fourth diode-connected PMOS transistor respectively.