Prefetching using hashed program counter
View Patent ↗Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.
1. A method for prefetching in a data processing system, the method comprising:
hashing a program counter value to produce a hashed program counter value, wherein the hashed program counter value has fewer bits than the program counter value;
propagating the hashed program counter value through a plurality of processor pipeline stages of a processor pipeline;
using the hashed program counter value for data prefetching in the data processing system, wherein the step of using the hashed program counter value for data prefetching in the data processing system comprises:
using the hashed program counter value to determine a stream identifier; and
using the stream identifier for prefetching in the data processing system;
wherein the step of using the hashed program counter value for data prefetching further includes using the hashed program counter value for strided stream detection in a data address stream of the processor pipeline.
2. A method of claim 1 , wherein the step of using the hashed program counter value to determine a stream identifier comprises:
combining the hashed program counter value and a second value to produce the stream identifier.
3. A method of claim 2 , wherein the second value comprises a register identifier.
4. A method of claim 3 , wherein the register identifier comprises a source register identifier.
5. A method of claim 2 , wherein the step of combining comprises:
performing at least one of a group consisting of a logic operation and an arithmetic operation using the hashed program counter value as a first operand and using the second value as a second operand.
6. A method of claim 1 , wherein the step of using the hashed program counter value for prefetching in the data processing system comprises:
using the hashed program counter value to determine if an instruction associated with the hashed program counter value has been allocated to a prefetch engine.
7. A method of claim 1 , wherein the hashed program counter value comprises four consecutive bits of the program counter value.
8. The method of claim 1 , further comprising:
using the detection of a strided stream to generate a prefetch address.
9. The method of claim 1 further comprising:
allocating a plurality of prefetch engines to detect strided streams in an address stream;
wherein the step of using the hashed program counter value for prefetching in the data processing system includes determining whether an instruction associated with the hashed program counter value is allocated to a prefetch engine of the plurality of prefetch engines.
10. The method of claim 1 wherein the step of using the hashed program counter value for prefetching in the data processing system includes using the hashed program counter value to identify a load instruction in the processor pipeline for detection of a strided stream in the address stream.
11. The method of claim 1 wherein the step of using the hashed program counter value for prefetching in the data processing system includes using the hashed program counter value to identify whether a load instruction associated with the hashed program counter value has an address that is part of a strided stream in the address stream.
12. The method of claim 1 wherein the step of using the hashed program counter value for prefetching in the data processing system further includes using the hashed program counter value in prefetch address generation.
13. The method of claim 1 wherein the step of prefetching comprises data prefetching.
14. The method of claim 1 wherein the plurality of processor pipeline stages includes an execute stage.
15. The method of claim 1 wherein the plurality of processor pipeline stages includes a decode stage.
16. The method of claim 1 wherein the plurality of processor pipeline stages includes a fetch stage.
17. The method of claim 2 further comprising:
propagating the second value through more than one processor pipeline stage of the processor pipeline.
18. A data processing system, comprising:
a program counter circuit, the program counter circuit providing a program counter value;
hashing circuitry, coupled to the program counter circuit, the hashing circuitry hashing the program counter value to produce a hashed program counter value, wherein the hashed program counter value has fewer bits than the program counter value;
a stage of a processor pipeline coupled to the hashing circuitry, the stage of the processor pipeline is used for instruction fetching, the stage of the processor pipeline receiving the hashed program counter value;
a second stage of the processor pipeline, coupled to the stage of the processor pipeline, the second stage of the processor pipeline is used for instruction execution, the second stage of the processor pipeline receiving the hashed program counter value via the stage; and
detection circuitry, coupled to the stage and the second stage of the processor pipeline, the detection circuitry using the hashed program counter value received via the stage and the second stage for stream identification in performing strided stream detection.
19. A data processing system of claim 18 , further comprising a third stage of the processor pipeline coupled to the stage and the second stage, the third stage used for instruction decoding, the third stage of the processor pipeline receiving the hashed program counter value via the stage, the second stage of the processor pipeline receiving- the hashed program counter value via the stage and the third stage.
20. A method for pipelining in a data processing system, the data processing system including a processor pipeline with a plurality of pipeline stages, the method comprising:
deriving a value from a program counter to produce a derived program counter value;
propagating the derived program counter value through at least one of the plurality of pipeline stages wherein the at least one stage includes a decode stage;
propagating a second value through at least one of the plurality of pipeline stages until the predetermined pipeline stage is reached;
propagating the derived program counter value through a second one of the plurality of pipeline stages, wherein the second one is characterized as an execution stage;
combining, after the propagating the derived program counter value and the propagating the second value, the derived program counter value and the second value to produce a stream identifier;
using the stream identifier for stream identification for prefetching in the data processing system.
21. A method of claim 20 , comprising:
propagating the derived program counter value through a fetch stage of the plurality of pipeline stages.
22. A method of claim 20 , comprising:
propagating the derived program counter value through more than half of the plurality of pipeline stages until a predetermined pipeline stage is reached.
23. A method of claim 20 , wherein the derived program counter value has fewer bits than the program counter.
24. A method of claim 20 , comprising:
propagating the second value through more than half of the plurality of pipeline stages until a predetermined pipeline stage is reached.
25. A method of claim 20 wherein the step of using the derived program counter value for prefetching further includes using the derived program counter value for strided stream detection in a data address stream of the processor pipeline.