Manufacturing method to construct semiconductor-on-insulator with conductor layer sandwiched between buried dielectric layer and semiconductor layers
View Patent ↗A method for treating exposed metal in a semiconductor wafer ( 301 ) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer ( 307 ) and a substrate ( 303 ), wherein a portion of the metal layer is exposed at the edge of the wafer. The exposed portion of the metal layer is then covered with a dielectric material ( 317 ).
1. A method for making a semiconductor device, comprising;
providing a wafer comprising a semiconductor substrate and a first dielectric layer;
forming a metal gate disposed over said first dielectric layer, said metal gate being indented with respect to said substrate and being near the edge of the wafer; and
forming a second dielectric layer which fills said indentation;
wherein the step of forming the second dielectric layer occurs before the step of forming the metal gate.
2. The method of claim 1 , wherein the gate is formed in an aperture created in the second dielectric layer.
3. The method of claim 2 , further comprising the step of forming the metal gate from a gate metal layer, and wherein the metal gate is formed by:
depositing the gate metal layer; and
subjecting the gate metal layer to chemical mechanical polishing.
4. A method for treating exposed metal during wafer processing, comprising:
providing a wafer equipped with a metal layer disposed between a substrate and a first dielectric layer, wherein said first dielectric layer comprises a first dielectric material, and wherein a portion of said metal layer is exposed at the edge of the wafer;
removing a portion of the metal layer such that the metal layer is indented with respect to the substrate and the first dielectric layer; and
backfilling the indentation with a second dielectric material.
5. The method of claim 4 , wherein the step of backfilling the indentation with a second dielectric material comprises:
depositing a layer of the second dielectric material over the wafer; and
subjecting the wafer to chemical mechanical polishing until the metal layer is exposed.
6. The method of claim 4 , wherein the first dielectric material is a high-k dielectric material.
7. The method of claim 4 , further comprising a buried oxide layer disposed between the substrate and the metal layer.
8. The method of claim 4 , wherein the wafer is an FDSOI wafer.
9. The method of claim 4 , wherein the wafer is an PDSOI wafer.
10. The method of claim 4 , wherein the wafer is a planar double gate device.
11. The method of claim 4 , wherein the metal layer comprises a gate.
12. The method of claim 4 , wherein the metal layer comprises an interconnect.
13. The method of claim 4 , further comprising a layer of a third dielectric material disposed between the metal layer and the semiconductor wafer.
14. The method of claim 13 , wherein the semiconductor wafer has a channel defined therein, and wherein the channel is adjacent to the layer of the third dielectric material.
15. A method for making a semiconductor device, comprising:
providing a semiconductor wafer having a first dielectric layer disposed thereon;
forming a second dielectric layer over the first dielectric layer, wherein said second dielectric layer extends to the edge of the wafer;
forming an opening in the second dielectric layer which exposes a portion of the first dielectric layer, said opening being disposed near the edge of the wafer; and
forming a metal gate in the opening.
16. The method of claim 15 , wherein the second dielectric layer extends from the metal gate to the edge of the wafer.
17. The method of claim 15 , further comprising the step of forming the metal gate from a metal gate layer, and wherein the metal gate is formed by:
depositing the metal gate layer; and
subjecting the metal gate layer to chemical mechanical polishing.
18. The method of claim 15 , wherein said semiconductor wafer has a channel defined therein, the channel being adjacent to the first dielectric layer.
19. The method of claim 15 , wherein the metal gate is formed by depositing a layer of metal over the opening, and subjecting the resulting structure to chemical mechanical polishing (CMP).