Integrated circuit having a low power mode and method therefor
View Patent ↗An integrated circuit ( 70 ) includes a first power supply bus ( 72 ) and a second power supply bus ( 74 ). The first power supply bus ( 72 ) provides a first power supply voltage (VDD) to a first plurality of circuit elements ( 12 and 76 ). The second power supply bus ( 74 ) provides a second power supply voltage (LVDD) to a second plurality of circuit elements ( 14 ), where the second power supply voltage is lower than the first power supply voltage. During a normal operating mode of the integrated circuit ( 70 ), the first power supply bus ( 72 ) provides the first power supply voltage to the first plurality of circuit elements ( 12 and 76 ) and the second power supply voltage is not provided to the second plurality of circuit elements ( 14 ). During a low power operating mode, the second power supply bus ( 74 ) provides the second power supply voltage to the second plurality of circuit elements ( 14 ) and the first power supply voltage is not provided to the first plurality of circuit elements ( 12 and 76 ).
1. An integrated circuit comprising:
a first power supply bus for providing a first power supply voltage to a first plurality of circuit elements; and
a second power supply bus for providing a second power supply voltage to a second plurality of circuit elements, the second power supply voltage being lower than the first power supply voltage;
wherein the first power supply bus provides the first power supply voltage to the first plurality of circuit elements during a normal operating mode of the integrated circuit, and wherein the second power supply voltage is not provided to the second plurality of circuit elements during the normal operating mode of the integrated circuit,
wherein the second power supply bus provides the second power supply voltage to the second plurality of circuit elements during a low power operating mode of the integrated circuit, and wherein the first power supply voltage is not provided to the first plurality of circuit elements during the low power operating mode of the integrated circuit; and
wherein when the integrated circuit is transitioning from the normal operating mode to the low power operating mode the first and second power supply voltages are provided by the first and second power supply buses at the same time for a first predetermined length of time.
2. The integrated circuit of claim 1 , wherein the first plurality of circuit elements comprises a first plurality of storage elements and the second plurality of circuit elements comprises a second plurality of storage elements, and wherein one of the first plurality of storage elements is coupled to a corresponding one of the second plurality of storage elements.
3. The integrated circuit of claim 2 wherein the first predetermined length of time is a length of time sufficient for a logic state of the one of the first plurality of storage elements to be transferred to the corresponding one of the second plurality of storage elements.
4. The integrated circuit of claim 3 , wherein the logic state of the one of the first plurality of storage elements is transferred to the corresponding one of the second plurality of storage elements in response to the second power supply voltage being provided to the second plurality of storage elements.
5. The integrated circuit of claim 1 wherein first plurality of circuit elements comprises a plurality of logics circuits and the second plurality of circuit elements comprises a second plurality of storage elements.
6. The integrated circuit of claim 4 , wherein the first power supply voltage is removed from the first plurality of storage elements at the end of the first predetermined length of time.
7. The integrated circuit of claim 6 , wherein when the integrated circuit is transitioning from the low power operating mode to the normal operating mode, the first and second power supply voltages are provided by the first and second power supply buses for a second predetermined length of time.
8. The integrated circuit of claim 7 wherein the second predetermined length of time is a length of time sufficient for a logic state of the one of the second plurality of storage e elements to be transferred to the corresponding one of the first plurality of storage elements.
9. The integrated circuit of claim 2 , wherein the one of the first plurality of storage elements comprising a first pair of cross-coupled inverters having first and second storage nodes, and the corresponding one of the second plurality of storage elements comprising a second pair of cross-coupled inverters having third and forth storage nodes; the integrated circuit further comprising: a first transistor having a first current electrode coupled to the first storage node, a second current electrode coupled to a ground terminal, and a control electrode coupled to the third storage node; and a second transistor having a first current electrode coupled to the third storage node, a second current electrode coupled to the ground terminal, and a control electrode coupled to the first storage node.
10. A method comprising:
providing a first power supply bus on an integrated circuit for conducting a first power supply voltage to a first plurality of circuits;
providing the first power supply voltage to the first plurality of circuits on the integrated circuit during a normal operating mode of the integrated circuit;
removing the first power supply voltage from the first power supply bus during a low power operating mode;
providing a second power supply bus on the integrated circuit for providing a second power supply voltage to a second plurality of circuits on the integrated circuit during the low power operating mode of the integrated circuit; and
removing the second power supply voltage from the second power supply bus during the normal operating mode; and
providing both the first power supply voltage and the second power supply voltage at the same time for a first predetermined time period when the integrated circuit transitions between the normal operating mode and the low power operating mode.
11. The method of claim 10 , wherein the first plurality of circuits comprise logic circuits and the second plurality of circuits comprise storage elements.
12. The method of claim 10 further comprising providing both the first power supply voltage and the second power supply voltage for a second predetermined time period when the integrated circuit transitions from the low power operating mode to the normal operating mode.
13. The method of claim 12 , further comprising transferring data between one of the second plurality of circuits to one of the first plurality of circuits during the first predetermined time period.
14. The method of claim 10 , further comprising transferring data between one of the first plurality of circuits to one of the second plurality of circuits during the first predetermined time period.
15. The method of claim 10 , wherein providing both the first power supply voltage and the second power supply voltage for a first predetermined time period further comprises automatically transferring data between one of the first plurality of circuits to one of the second plurality of circuits in response to providing both the first and second power supply voltages.
16. The method of claim 10 , wherein the first plurality of circuits comprises a first plurality of storage elements and the second plurality of circuits comprises a second plurality of storage elements.
17. An integrated circuit having a normal operating mode and a low power mode, the integrated circuit comprising:
a first latch circuit having an input terminal for receiving a data signal, a power supply terminal for receiving a first power supply voltage, and an output terminal; and
a second latch circuit having an input terminal coupled to the output terminal of the first latch circuit, a power supply terminal for receiving a second power supply voltage different from the first power supply voltage, and an output terminal coupled to the input terminal of the first latch circuit;
wherein during the normal operating mode the first power supply voltage is provided to the first latch circuit and the second power supply voltage is not provided to the second latch circuit;
wherein during the low power mode the second power supply voltage is provided to the second latch circuit and the first power supply voltage is not provided to the first latch circuit; and
wherein when the integrated circuit is transitioning from the normal operating mode to the low power mode the second power supply voltage is provided to the second latch circuit and the first power supply voltage is provided to the first latch circuit at the same time for a first predetermined length of time and then the first power supply voltage is removed from the first latch circuit, the first predetermined length of time sufficient for a logic state of the first latch circuit to be transferred to the second latch circuit.
18. The integrated circuit of claim 17 , wherein the first and second latch circuits each comprise a pair of cross-coupled inverters having first and second storage nodes, the integrated circuit further comprising: a first transistor having a first current electrode coupled to the first storage node of the first latch circuit, a second current electrode coupled to a ground terminal, and a control electrode coupled to the first storage node of the second latch circuit; and a second transistor having a first current electrode coupled to the first current electrode of the second latch circuit, a second current electrode coupled to the ground terminal, and a control electrode coupled to the first storage node of the first latch circuit.
19. The integrated circuit of claim 17 , wherein the second power supply voltage is lower than the first power supply voltage.
20. The integrated circuit of claim 17 , wherein when the integrated circuit is transitioning from the low power mode to the normal operating mode the second power supply voltage is provided to the second latch circuit and the first power supply voltage is provided to the first latch circuit at the same time for a second predetermined length of time and then the second power supply voltage is removed from the second latch circuit, the second predetermined length of time sufficient for a logic state of the second latch circuit to be transferred to the first latch circuit.