Clock delay compensation circuit
View Patent ↗A clock delay compensation circuit for an integrated circuit having a first voltage domain and a second voltage domain, has a first delay element that receives a clock signal and generates a first delayed clock signal, and a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal. The first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.
1. A clock delay compensation circuit for an integrated circuit having at least a first voltage domain and a second voltage domain, the clock delay compensation circuit comprising:
a first delay element that receives a clock signal and generates a first delayed clock signal; and
a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal, wherein the first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain, wherein a multiplexer select signal, which is input to the multiplexer to select between the clock signal and the first delayed clock signal, includes a regulator ramp counter signal.
2. The clock delay compensation circuit of claim 1 , wherein the first voltage domain comprises a substantially constant voltage domain.
3. The clock delay compensation circuit of claim 2 , wherein the second voltage domain comprises a variable voltage domain.
4. The clock delay compensation circuit of claim 3 , wherein the voltage of the second voltage domain is alterable via software.
5. The clock delay compensation circuit of claim 3 , wherein the clock input signal is a substantially constant clock signal for a given frequency.
6. The clock delay compensation circuit of claim 5 , wherein the substantially constant clock signal is transmitted from the first voltage domain to the second voltage domain.
7. The clock delay compensation circuit of claim 6 , further comprising:
a plurality of second delay elements connected in series, wherein an output of each of the second delay elements is input to a next delay element in the series and to the multiplexer.
8. The clock delay compensation circuit of claim 7 , wherein the number of multiplexer inputs is equal to the number of first and second delay elements plus one.
9. The clock delay compensation circuit of claim 7 , wherein as a voltage level of the variable voltage domain increases, an increasingly delayed clock signal is selected.
10. The clock delay compensation circuit of claim 1 , further comprising:
a counter that counts a number of voltage steps that a voltage regulator encounters before stabilizing.
11. The.clock delay compensation circuit of claim 10 , wherein the counter has a clock with a frequency corresponding to a rate at which the output of the voltage regulator changes.
12. The clock delay compensation circuit of claim 1 , wherein the delay element comprises at least one buffer.
13. A clock delay compensation circuit for an integrated circuit having a first, constant voltage domain and a second, variable voltage domain, wherein the first voltage domain operates in accordance with a substantially constant clock signal and the second voltage domain operates in accordance with a variable clock signal, the clock delay compensation circuit comprising:
a first delay element that receives the substantially constant clock signal and generates a first delayed clock signal; and
a multiplexer that receives the substantially constant clock signal and the first delayed clock signal and generates the variable clock signal, wherein the first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain, and wherein a multiplexer select signal, which is input to the multiplexer to select between the clock signal, and the first delayed clock signal, includes a regulator ramp counter signal.
14. The clock delay compensation circuit of claim 13 , further comprising:
a plurality of second delay elements connected in series, wherein an output of each of the second delay elements is input to a next delay element in the series and to the multiplexer.
15. The clock delay compensation circuit of claim 14 , wherein as the voltage level of the variable voltage domain increases, an increasingly delayed clock signal is selected.
16. The clock delay compensation circuit of claim 13 , further comprising:
a counter for generating the regulator ramp counter signal that counts a number of voltage steps that a voltage regulator encounters before stabilizing.
17. The clock delay compensation circuit of claim 16 , wherein the counter has a clock with a frequency corresponding to a rate at which the output of the voltage regulator changes.
18. The clock delay compensation circuit of claim 13 , wherein the delay element comprises at least one buffer element.