Circuit and method for latch bypass
View Patent ↗A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.
1. A device comprising:
a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value;
a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value, the latch stage further comprising:
a NOR logic stage having a first input to receive the bypass value, a second input to receive a representation of the second data value, and an output; and
an inverter logic stage having an input coupled to the output of the NOR logic stage and an output coupled to the second input of the NOR logic stage and the second input of the second combinatorial logic stage; and
a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.
2. The device of claim 1 , wherein the first predetermined value and the second predetermined value are the same value.
3. The device of claim 1 , wherein the first and second combinatorial logic stages comprise NAND logic stages.
4. The device of claim 1 , wherein:
when the bypass value is asserted:
the output of the first combinatorial logic stage provides the representation of the first data value; and
the output of the latch stage provides the second predetermined value; and when the bypass value is not asserted:
the output of the first combinatorial logic stage provides the first predetermined value; and
the output of the latch stage provides a latched representation of the second data value.
5. The device of claim 1 , wherein the first data value comprises a bit value of test data and the second data value comprises a bit value of operation data.
6. A device comprising:
a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value;
a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value;
a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output; and
the latch stage further comprising:
a first voltage reference;
a second voltage reference;
a first transistor having a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to a first node, and a control electrode to receive a clock signal;
a second transistor having a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to the first node, and a control electrode to receive a representation of the bypass value;
a third transistor having a first current-carrying electrode coupled to the first node, a second current-carrying electrode coupled to a second node and a control electrode to receive the second data value;
a fourth transistor having a first current-carrying electrode coupled to the second voltage reference, a second current carrying electrode coupled to the second node and a control electrode to receive the second data value;
a first inverter stage having an input coupled to the second node and an output;
a second inverter stage having an input coupled to the output of the first inverter stage and an output coupled to the second node; and
wherein the second node comprises the output of the latch stage.
7. The device of claim 6 , wherein the first, second and third transistors comprise p-type transistors and the fourth transistor comprises an n-type transistor.
8. A method comprising:
receiving, at a first combinatorial logic stage, a first data value and a bypass value;
receiving, at a latch stage, a second data value and the bypass value;
providing, at an output of the first combinatorial logic stage, a first output value comprising one of a representation of the first data value or a first predetermined value based on the bypass value;
providing, at an output of the latch stage, a second output value comprising one of a latched representation of the second data value or a second predetermined value based on the bypass value;
receiving, at a second combinatorial logic stage, the first output value and the second output value; and
providing, at an output of the second combinatorial logic stage, a third output value based on the first output value and the second output value;
wherein receiving, at the latch stage, the second data value and the bypass value comprises:
receiving, at a NOR logic stage of the latch stage, the bypass value and the second data value; and
providing a fourth output value at an output of the NOR logic stage based on the bypass value and the second data value; and
wherein providing, at the output of the latch stage, the second output value comprises:
receiving, at an inverter of the latch stage, the fourth output value; and
providing a fifth output value at an output of the inverter, the fifth output value comprising a representation of the fourth output value, and wherein the second output value comprises the fifth output value.
9. The method of claim 8 , wherein the first predetermined value and the second predetermined value are the same value.
10. The method of claim 8 , wherein the first and second combinatorial logic stages comprise NAND logic stages.
11. The method of claim 10 , wherein:
the first output value comprises a representation of the first data value and the second output value comprises the second predetermined value when the bypass value is asserted; and
the first output value comprises the first predetermined value and the second output value comprises the latched representation of the second data value when the bypass value is not asserted.
12. The method of claim 8 , wherein the first data value comprises a bit value of test data and the second data value comprises a bit value of operation data.
13. The method of claim 8 , wherein only two gate delays occur between receiving, at the latch stage, the second data value and the bypass value and providing, at an output of the second combinatorial logic stage, a third output value based on the first output value and the second output value.
14. A device comprising:
an operational data source;
a test data source; and
a multiplexer having a first input coupled to the operational data source, a second input coupled to the test data source, a third input to receive a bypass signal, and an output to provide one of a first data value representative of a value received at the first input or a second data value representative of a value received at the second input based on a value of the bypass signal, wherein the multiplexer comprises a latch stage having a first input coupled to the first input of the multiplexer, a second input coupled to receive the bypass signal, and an output coupled to the output of the multiplexer, wherein the multiplexer is configured so that there is only a first two gate delay between the first input of the multiplexer and the output of the multiplexer via the latch stage and there is only a second two gate delay between the second input and the output of the multiplexer, the first two gate delay comprising a first combinatorial logic stage and a second combinatorial logic stage and the second two gate delay comprising a transistor configuration and the second combinatorial logic stage.
15. The device of claim 14 , wherein the multiplexer comprises:
the first combinatorial logic stage having a first input to receive the first data value, a second input to receive the bypass signal and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass signal;
a latch stage having a first input to receive the second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value and a second predetermined value based on the bypass signal; and
the second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.
16. The device of claim 15 , wherein the latch stage comprises:
a first voltage reference;
a second voltage reference;
a first transistor having a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to a first node, and a control electrode to receive a clock signal;
a second transistor having a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to the first node, and a control electrode to receive a representation of the bypass signal;
a third transistor having a first current-carrying electrode coupled to the first node, a second current-carrying electrode coupled to a second node and a control electrode to receive the second data value;
a fourth transistor having a first current-carrying electrode coupled to the second voltage reference, a second current carrying electrode coupled to the second node and a control electrode to receive the second data value;
a first inverter stage having an input coupled to the second node and an output;
a second inverter stage having an input coupled to the output of the first inverter stage and an output coupled to the second node; and
wherein the second node comprises the output of the latch stage.
17. The device of claim 15 , wherein the latch stage comprises:
a NOR logic stage having a first input to receive the bypass value, a second input to receive a representation of the second data value, and an output; and
an inverter logic stage having an input coupled to the output of the NOR logic stage and an output coupled to the second input of the NOR logic stage and the second input of the second combinatorial logic stage.
18. The device of claim 6 , wherein the first and second combinatorial logic stages comprise NAND logic stages.
19. The device of claim 6 , wherein:
when the bypass value is asserted:
the output of the first combinatorial logic stage provides the representation of the first data value; and
the output of the latch stage provides the second predetermined value; and when the bypass value is not asserted:
the output of the first combinatorial logic stage provides the first predetermined value; and
the output of the latch stage provides a latched representation of the second data value.
20. The device of claim 6 , wherein the first data value comprises a bit value of test data and the second data value comprises a bit value of operation data.