Granted Patent B2

US 7,446,006 · App. 11/226,826 · Granted Nov 4, 2008

Abstract

Claims (14)

1. A semiconductor fabrication process, including

forming a gate electrode overlying a gate dielectric overlying a substrate of a wafer;

forming a liner dielectric layer including vertical portions adjacent sidewalls of the gate electrode and horizontal portions overlying an upper surface of the semiconductor substrate;

forming an extension spacer adjacent a vertical portion and overlying a horizontal portion of the liner dielectric layer;

following said forming of the extension spacer, removing exposed portions of the liner dielectric layer to form a liner dielectric structure covered by the extension spacer and to expose portions of the substrate;

etching back the extension spacer to uncover extremities of the liner dielectric structure;

following said etching back, removing at least part of the exposed extremities of the liner dielectric structure; and

forming silicide on the exposed portions of the substrate.

2. The method of claim 1 , wherein forming the liner dielectric layer comprises depositing a conformal oxide on the wafer.

3. The method of claim 2 , wherein forming the extension spacer comprises depositing a silicon nitride layer on the liner dielectric layer and anisotropically etching the silicon nitride layer.

4. The method of claim 3 , further comprising, prior to said etching back, depositing a metal layer non selectively over the wafer.

5. The method of claim 4 , wherein depositing the metal layer comprises sputter depositing the metal layer.

6. The method of claim 1 , wherein said removing at least part of the exposed extermities includes sputter cleaning the wafer.

7. The method of claim 6 , wherein said sputter cleaning comprises radio frequency sputtering using argon ions.

Assignments (34)