Transistor devices with nano-crystal gate structures
View Patent ↗Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
1. A semiconductor device comprising:
a semiconductor substrate having an upper surface;
a gate stack on the upper surface, wherein the gate stack comprises
a gate dielectric on the upper surface, the gate dielectric having therein a layer of spaced-apart nano-crystals of a material adapted to reversibly receive and store charge,
first and second impurity blocking layers over the gate dielectric, wherein the first impurity blocking layer is in contact with the gate dielectric, the first impurity blocking layer comprises FeBSi, the second impurity blocking layer is in contact with the first impurity blocking layer, and the second impurity blocking layer comprises a different material from FeBSi, and
a gate conductor layer over the first and second impurity blocking layers; and
spaced-apart source-drain regions laterally disposed on either side of the gate stack.
2. The semiconductor device of claim 1 , wherein the second impurity blocking layer comprises a material selected from a group consisting of Al 2 O 3 , TiN, TiO 2 , CO 3 O 4 , MoSiN, W, TaC, and Si 3 N 4 .
3. The semiconductor device of claim 2 , wherein the second impurity blocking layer comprises TiN.
4. The semiconductor device of claim 2 , wherein the second impurity blocking layer comprises Si 3 N 4 .
5. The semiconductor device of claim 1 , wherein the nano-crystals are passivated.
6. The semiconductor device of claim 1 , wherein the nano-crystals are, on average, spaced apart by about 30 Angstrom units or more.
7. The semiconductor device of claim 1 , wherein at least one of the first and second impurity blocking layers has a thickness in the range of about 10 to 500 Angstrom units.
8. The semiconductor device of claim 1 , wherein the gate dielectric comprises a metal oxide.
9. The semiconductor device of claim 8 , wherein the metal oxide comprises oxides of hafnium or zirconium or combinations thereof.
10. A semiconductor device comprising:
a semiconductor substrate having an upper surface;
a gate stack on the upper surface, wherein the gate stack comprises
a gate dielectric having therein a first gate dielectric region on the upper surface, a layer of spaced-apart nano-crystals of a material adapted to reversibly receive and store charge on the first gate dielectric region, and a second gate dielectric region over the nano-crystals and the first gate dielectric region,
a first impurity blocking layer in contact with the gate dielectric, wherein the first impurity blocking layer comprises FeBSi,
a second impurity blocking layer in contact with the first impurity blocking layer, wherein the second impurity blocking layer comprises a material different from FeBSi, and
a gate conductor layer over the second impurity blocking layer; and
spaced-apart source-drain regions laterally disposed on either side of the gate stack.
11. The semiconductor device of claim 10 , wherein the second impurity blocking layer includes a material selected from a group of materials that consists of Al 2 O 3 , TiN, TiO 2 , CO 3 O 4 , MoSiN, W, TaC, and Si 3 N 4 .
12. The semiconductor device of claim 10 , wherein the first gate dielectric region comprises a metal oxide.
13. The semiconductor device of claim 12 , wherein the metal oxide comprises oxides of hafnium or zirconium or combinations thereof.
14. The semiconductor device of claim 10 , wherein at least one of the first impurity blocking layer and the second impurity blocking layer has a thickness in the range of about 10 to 500 Angstrom units.
15. The semiconductor device of claim 10 , wherein the nano-crystals are, on average, spaced apart by about 30 Angstrom units or more.
16. A semiconductor device, comprising:
a semiconductor substrate having a principal surface;
spaced-apart source and drain regions separated by a channel region at the principal surface;
a multilayered gate structure located over the channel region, wherein the multilayered gate structure comprises;
a first gate dielectric region;
a second gate dielectric region overlying the first gate dielectric region and having an interface with the first gate dielectric region;
nano-crystals of a conductive material disposed at the interface between the first and second dielectric gate regions;
a first impurity blocking layer in contact with the second gate dielectric region, wherein the first impurity blocking layer includes an amorphous dielectric FeBSi; and
a second impurity blocking layer in contact with the first impurity blocking layer, wherein the second impurity blocking layer includes a different material from FeBSi; and
a first conductor disposed on the second impurity blocking layer.
17. The semiconductor device of claim 16 , wherein the second impurity blocking layer includes a material selected from a group of materials that consists of Al 2 O 3 , TiN, TiO 2 , CO 3 O 4 , MoSiN, W, TaC, and Si 3 N 4 .
18. The semiconductor device of claim 17 , wherein the second impurity blocking layer includes TiN.
19. The semiconductor device of claim 17 , wherein the second impurity blocking layer includes Si 3 N 4 .