Clock tree adjustable buffer
View Patent ↗An adjustable buffer including a series of P-channel devices having current paths coupled between a first voltage supply and at least one output node, and a series of N-channel devices having current paths coupled between the output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the output node. The selectable connections may be defined in an integrated circuit mask or may be electronic switches. The P- and N-channel devices may be in a balanced configuration or an imbalanced configuration. The P- and N-channel devices may form an inverting buffer or a non-inverting buffer.
1. A buffer with programmable delay, comprising:
an input node;
a first voltage supply node receiving a first supply voltage;
a second voltage supply node receiving a second supply voltage;
a plurality of pull-up devices having current paths coupled between said first voltage supply node and at least one output node and having a corresponding first plurality of gates, wherein each of said first plurality of gates is coupled to a selected one of said input node and said second voltage supply collectively forming a first plurality of programmable connections; and
a plurality of pull-down devices having current paths coupled between said at least one output node and said second voltage supply node and having a corresponding second plurality of gates, wherein each of said second plurality of gates is coupled to a selected one of said input node and said first voltage supply node collectively forming a second plurality of programmable connections;
wherein said first and second plurality of programmable connections are programmed to adjust delay from said input node to said at least one output node.
2. The buffer of claim 1 , wherein said first and second plurality of programmable connections comprise conductive connections defined in an integrated circuit mask.
3. The buffer of claim 1 , wherein said first and second plurality of programmable connections comprise electronic switches.
4. The buffer of claim 1 , wherein said plurality of pull-up devices and said plurality of pull-down devices comprise a balanced configuration to enable symmetrical programming of rising edge transition delays and falling edge transition delays.
5. The buffer of claim 1 , wherein said plurality of pull-up devices and said plurality of pull-down devices comprise an imbalanced configuration to enable asymmetrical programming of rising edge transition delays and falling edge transition delays.
6. The buffer of claim 1 , wherein said plurality of pull-up devices and said plurality of pull-down devices comprise complementary metal-oxide semiconductor transistors.
7. The buffer of claim 1 , wherein said plurality of pull-up devices and said plurality of pull-down devices comprise an inverting buffer.
8. The buffer of claim 1 , wherein said plurality of pull-up devices and said plurality of pull-down devices comprise a non-inverting buffer.
9. The buffer of claim 1 , wherein said plurality of pull-up devices comprises a first plurality of pull-up devices having current paths coupled between said first voltage supply node and a first output node and a second plurality of pull-up devices having current paths coupled between said first voltage supply node and a second output node, and wherein said plurality of pull-down devices comprises a first plurality of pull-down devices having current paths coupled between said first output node and said second voltage supply node and a second plurality of pull-down devices having current paths coupled between said second output node and said second voltage supply node.
10. The buffer of claim 1 , wherein each of said plurality of pull-up devices comprises a P-channel device and wherein each of said plurality of pull-down devices comprise N-channel devices.
11. The buffer of claim 1 , wherein said current paths of said plurality of pull-up devices are coupled in series between said first voltage supply node and said at least one output node, and wherein said current paths of said plurality of pull-down devices are coupled in series between said second voltage supply node and said at least one output node.
12. The buffer of claim 1 , wherein said each of said first plurality of programmable connections comprises a selectable connection and wherein each of said second plurality of programmable connections comprises a selectable connection.
13. The buffer of claim 1 , wherein said plurality of pull-up devices comprises a first number of pull-up devices and wherein said plurality of pull-down devices comprises a second number of pull-down devices wherein said first and second numbers are equal.
14. The buffer of claim 1 , wherein said plurality of pull-up devices comprises a first number of pull-up devices and wherein said plurality of pull-down devices comprises a second number of pull-down devices wherein said first and second numbers are different.
15. The buffer of claim 1 , wherein:
said plurality of pull-up devices comprises first and second pull-up devices and wherein said plurality of pull-down devices comprises first and second pull-down devices;
wherein said gate of said first pull-up device is coupled to said second voltage supply, wherein said control electrode of said second pull-down device is coupled to said first voltage supply, and wherein said gates of said second pull-up device and said first pull-down device are both coupled to said input node for a relatively small delay configuration;
wherein said gate of said second pull-up device is coupled to said second voltage supply, wherein said gate of said first pull-down device is coupled to said first voltage supply, and wherein said gates of said first pull-up device and said second pull-down device are both coupled to said input node for a medium delay configuration; and
wherein said gates of said first and second pull-up devices and said first and second pull-down devices are coupled together and to said input node for a relatively large delay configuration.
16. A method of providing a buffer and programming delay of the buffer, comprising:
providing an input node and at least one output node;
providing a first voltage supply node for receiving a first supply voltage and providing a second voltage supply node for receiving a second supply voltage;
providing a plurality of pull-up devices each having a current path and a gate;
providing a plurality of pull-down devices each having a current path and a gate; and
electrically coupling each gate of each of the plurality of pull-up devices to either one of the input node and the second voltage supply node and electrically coupling each gate of each of the plurality of pull-down devices to either one of the input node and the first voltage supply node to adjust delay from the input node to the at least one output node.
17. The method of claim 16 , wherein said coupling each gate of each of the plurality of pull-up devices and coupling each gate of each of the plurality of pull-down devices comprises defining conductive connections in an integrated circuit mask.
18. The method of claim 16 , wherein said coupling each gate of each of the plurality of pull-up devices and coupling each gate of each of the plurality of pull-down devices comprises providing electronic switches.
19. The method of claim 16 , wherein said coupling each gate of each of the plurality of pull-up devices and coupling each gate of each of the plurality of pull-down devices comprises coupling in a balanced configuration to provide symmetrical programming between rising and falling edge transition delays.
20. The method of claim 16 , wherein said coupling each gate of each of the plurality of pull-up devices and coupling each gate of each of the plurality of pull-down devices comprises coupling in an imbalanced configuration to provide asymmetrical programming between rising and falling edge transition delays.