IP Library Granted Patent US 7,434,009
Granted Patent B2
US 7,434,009 · App. 10/955,220 · Granted Oct 7, 2008

Apparatus and method for providing information to a cache module using fetch bursts

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Quick Facts
Patent No.
US 7,434,009
App. No.
10/955,220
Granted
Oct 7, 2008
Kind
B2
Abstract

Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.

Claims (23)

1. A method for providing information to a cache module, the method comprising the stages of: simultaneously receiving multiple requests to retrieve multiple mandatory information units to a cache module; determining, before fetching a first mandatory data unit and a second mandatory data unit whether the first mandatory unit and the second mandatory data unit can be fetched during a single fetch burst; performing a single fetch burst if a memory space retrievable during a single fetch burst comprises the first and second mandatory data units; and performing multiple fetch bursts if the memory space does not comprise the first and the second mandatory data units.

2. The method of claim 1 wherein the stage of receiving requests to retrieve multiple information units to a cache module is preceded by a stage of determining that multiple cache miss occur.

3. The method of claim 1 wherein the determining comprises determining at least one characteristic of a memory space retrievable during the single fetch burst in response to a location of the first mandatory data unit and in response to a location of the second mandatory data unit.

4. The method according to claim 3 wherein the determining comprises determining at least one characteristic selected from a group consisting of a size of the fetch burst and a starting address of the fetch burst.

5. The method of claim 1 further comprising performing speculative fetch operations.

6. The method of claim 1 wherein at least one fetch burst comprises a speculative fetch operation.

7. The method of claim 6 wherein speculative information units associated with different mandatory information units are fetched in an interlaced manner.

8. The method of claim 1 wherein speculative information units associated with different mandatory information units are fetched in an interlaced manner.

9. The method according to claim 1 wherein the determining comprises determining an order of fetch operations within a fetch burst in response to a location of at least one mandatory data unit out of the first and second mandatory data units.

10. An apparatus for providing information to a cache module, the apparatus comprises:

logic, adapted to generate an indication that a retrieval of a first and second mandatory data units is required in response to a simultaneous reception of two data requests that results in cache misses

a controller, coupled to the cache logic, adapted to receive the indication and in response to:

determine, before initiating at least one fetch burst that comprises fetching a first mandatory data unit and a second mandatory data unit, whether the first mandatory unit and the second mandatory data unit can be fetched during a single fetch burst;

initiate a single fetch burst if a memory space retrievable during a single fetch burst comprises the first and second mandatory data units; and initiate multiple fetch bursts if the memory space does not comprise the first and the second mandatory data units.

11. The apparatus of claim 10 wherein at least one characteristic of a memory space retrievable during a fetch burst is responsive to a location of said memory space.

12. The apparatus of claim 10 wherein the controller is further adapted to initiate speculative fetch operations.

13. The apparatus of claim 10 wherein at least one fetch burst comprises a speculative fetch operation.

14. The apparatus of claim 10 wherein the controller is adapted to initiate speculative fetch operations associated with different mandatory fetch operation in an interlaced manner.

15. The apparatus of claim 10 further comprising the cache module.

16. The apparatus of claim 15 wherein the cache module is coupled to the logic.

17. The apparatus according to claim 10 wherein the controller is adapted to determine at least one characteristic of a memory space retrievable during the single fetch burst in response to a location of the first mandatory data unit and in response to a location of the second mandatory data unit.

18. The apparatus according to claim 17 wherein the controller is adapted to determine at least one characteristic selected from a group consisting of a size of the fetch burst and a starting address of the fetch burst.

19. The apparatus according to claim 10 wherein the controller is adapted to determine an order of fetch operations within a fetch burst in response to a location of at least one mandatory data unit out of the first and second mandatory data units.

Assignments (25)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 048387/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2019
From: NXP USA, INC.
To: VLSI TECHNOLOGY LLC
Reel/Frame 048389/0060 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0807 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 12, 2009
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To: CITIBANK, N.A.
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SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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From: GODIN, KOSTANTIN; ANSCHEL, MOSCHE; EFRAT, JACOB; ROSENSHEIN, ZVIKA; ZAMSKY, ZIV
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