Plastic packaged device with die interface layer
View Patent ↗Structure and method are provided for plastic encapsulated semiconductor devices having a buffer layer of low dielectric constant and/or low loss tangent material separating the die surface from the plastic encapsulation. Semiconductor wafers with substantially completed SC die are coated with the buffer layer. The buffer layer is patterned to expose the die bonding pads but leave the buffer layer over some or all of the other die metallization. The die are then separated, mounted on a lead-frame or other support, wire bonded or otherwise coupled to external leads, and encapsulated. The plastic encapsulation surrounds the die and the buffer layer, providing a solid structure. The buffer layer reduces the parasitic capacitance, cross-talk and loss between metallization regions on the die. An optional sealing layer may also be provided at the wafer stage between the buffer layer and the plastic encapsulation to mitigate any buffer layer porosity.
1. A method of providing a semiconductor die, the semiconductor die configured to operate at at least a first predetermined operating frequency, the method comprising:
providing a die having a principal surface with conductive interconnections and bonding pads thereon;
covering at least a portion of the principal surface of the die with a buffer layer material to form a buffer layer;
encapsulating the die with an encapsulant such that the encapsulant substantially surrounds the die and the upper surface of the encapsulant is substantially exposed; and
patterning the buffer layer to substantially expose regions on the bonding pads to be used for coupling the die to external leads but leaving the buffer layer over at least some of the conductive interconnections;
wherein the buffer layer material has at least one of the following characteristics: (i) a dielectric constant less than the dielectric constant of the encapsulant, and (ii) a loss tangent less than the loss tangent of the encapsulant at the first predetermined operating frequency.
2. The method of claim 1 wherein the dielectric constant of the buffer layer material is less than approximately 3.0.
3. The method of claim 1 wherein the step of covering comprises coating substantially all of the principal surface of the die with a buffer layer material to form a buffer layer having a substantially uniform thickness.
4. The method of claim 1 wherein the dielectric constant of the buffer layer material is less than the dielectric constant of the encapsulant, and the loss tangent of the buffer layer material is less than the loss tangent of the encapsulant at the first predetermined operating frequency.
5. The method of claim 1 wherein the semiconductor die produces a fringing field when operating at a predetermined frequency, and wherein the step of covering comprises coating at least a portion of the principal surface of the die with a buffer layer material to form a buffer layer having a thickness sufficient to substantially contain the fringing field.
6. A method of providing a semiconductor die comprising:
providing a die having a principal surface with conductive interconnections and bonding pads thereon;
covering at least a portion of the principal surface of the die with a buffer layer material to form a buffer layer;
encapsulating the die with an encapsulant;
patterning the buffer layer to substantially expose regions on the bonding pads to be used for coupling the die to external leads but leaving the buffer layer over at least some of the conductive interconnections; and
after the patterning step, forming a sealing layer on an outer surface of the buffer layer;
wherein the buffer layer material has at least one of the following characteristics: (i) a dielectric constant less than the dielectric constant of the encapsulant, and (ii) a loss tangent less than the loss tangent of the encapsulant.
7. The method of claim 6 wherein the step of forming a sealing layer comprises depositing a sealant onto a surface of the buffer layer, the sealant selected from the group consisting of SiO 2 , polyimide, and parylene.
8. The method of claim 6 wherein the step of forming a sealing layer comprises exposing the buffer layer to a catalyst to decrease the permeability of the buffer layer to moisture.