System and method for memory array access with fast address decoder
View Patent ↗A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
1. A method of operating a memory having a wordline driver, a first array, a second array, a third array, and a fourth array, comprising:
summing a first set of bits of a first operand and a corresponding set of bits of a second operand to obtain a pair of selection bits;
providing a first plurality of bits of the first operand;
providing a second plurality of bits of the second operand;
providing a third plurality of bits of the first operand;
providing a fourth plurality of bits of the second operand;
decoding a value that is based on the first plurality of bits and the second plurality of bits to provide a first decoded value to the wordline driver;
decoding a value that is based on the first plurality of bits and the second plurality of bits to provide a second decoded value to the wordline driver;
decoding a value that is based on the third plurality of bits and the fourth plurality of bits to provide a third decoded value to the wordline driver;
decoding a value that is based on the third plurality of bits and the fourth plurality of bits to provide a fourth decoded value to the wordline driver;
using the wordline driver to enable a wordline of the first array selected by the first and third decoded values, a wordline of the second array selected by the first and fourth decoded values, a wordline of the third array selected by the second and third decoded values, and a wordline of the fourth array selected by the second and fourth decoded values;and
using the pair of selection bits to select one of the first, second, third, and fourth arrays for providing an output corresponding to the sum of the first set of bits and the corresponding set of bits.
2. The method of claim 1 , wherein the memory is characterized as a cache, the method further comprising providing the output as a TAG value from a TAG array of the cache.
3. The method of claim 1 , the step of summing the first set of bits of the first operand and the corresponding bits of the second operand is performed concurrently with the steps of decoding to provide the first, second, third, and fourth decoded values.
4. A data processing system for providing a TAG having a memory comprising a wordline driver, a first array, a second array, a third array, and a fourth array, comprising:
an adder that adds a first plurality of bits that comprise a subset of a first operand to a second plurality of bits that comprise a subset of a second operand and provides a selection set of bits that is fewer in number than the first plurality of bits;
a first decoder coupled to receive a first set of bits that is a subset of the first plurality of bits and a second set of bits that is a subset of the second plurality of bits, and coupled to provide a first decoded value based on the first set of bits and the second set of bits and a second decoded value based on the first set of bits and the second set of bits; and
a second decoder coupled to receive a third set of bits of that is a subset of the first plurality of bits and a fourth set of bits that is a subset of the second plurality of bits, and coupled to provide a third decoded value based on the third set of bits and the fourth set of bits and a fourth decoded value based on the third set of bits and the fourth set of bits; and
a multiplexer coupled to the first, second, third, and fourth arrays and receives the selection set of bits;
wherein:
the wordline driver is coupled to receive the first decoded value, the second decoded value, the third decoded value, and the fourth decoded value, and coupled to enable one wordline of each of the first, second, third, and fourth arrays; and
the multiplexer selects one of the first, second, third, and fourth arrays for providing the TAG.
5. The data processing system of claim 4 , wherein the adder adds the first plurality of bits to the second plurality of bits and provides the selection set of bits concurrently with the first and second decoders providing the first, second, third, and fourth decoded values and the wordline driver enabling one wordline of each of the first, second, third, and fourth arrays.
6. The data processing system of claim 5 , wherein the multiplexer selects the one wordline of the first array based on the first decoded value and the third decoded value, the one wordline of the second array based on the first decoded value and the fourth decoded value, the one wordline of the third array based on the second decoded value and the third decoded value, and the one wordline of the fourth array based on the second decoded value and the fourth decoded value.