Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same
View Patent ↗One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
1. A process for forming an electronic device comprising:
forming a gate dielectric layer over a first portion and a second portion of the substrate;
forming a first layer of a gate stack over the gate dielectric layer, wherein the first layer comprises a first element that is a metallic element, and lies immediately adjacent to the gate dielectric layer over the first portion of the substrate;
incorporating an impurity into the first layer after forming the first layer over the gate dielectric layer, wherein the impurity comprises a second element within Group 2 or 13 of the Periodic Table;
forming a second layer of the gate stack over gate dielectric layer, wherein the second layer lies immediately adjacent to the gate dielectric layer over the second portion of the substrate, and after forming the first layer and forming the second layer, the second layer overlies the first layer over the first portion of the substrate;
forming a third layer of the gate stack over the first layer and the second layer;
patterning the gate stack, wherein after patterning the gate stack, a first gate electrode overlies the first portion of the substrate, and a second gate electrode overlies the second portion of the substrate;
forming a first source/drain region over the first portion of the substrate, wherein after forming the first source/drain region, a first transistor lies over the first portion of the substrate and includes the first source/drain and the first gate electrode; and
forming a second source/drain region over the second portion of the substrate, wherein after forming the second source/drain region, a second transistor lies over the second portion of the substrate and includes the second source/drain and the second gate electrode.
2. The process of claim 1 , wherein the impurity comprises boron-containing species.
3. The process of claim 1 , wherein incorporating the impurity comprises implanting the impurity.
4. The process of claim 1 , further comprising:
removing the first layer from the second portion of the substrate before forming the second layer.
5. The process of claim 1 , wherein: the first transistor includes a PMOS transistor;
the first layer substantially determines the work function of the PMOS transistor;
the second transistor includes an NMOS transistor;
the second layer substantially determines the work function of the NMOS transistor; and
the second gate electrode does not include the first layer.
6. The process of claim 1 ,
wherein forming the second layer is performed before incorporating the impurity.
7. A process for forming an electronic device comprising:
forming a gate dielectric layer over a first and a second portion of a substrate;
forming a first layer of the gate stack over the gate dielectric layer, wherein the first layer includes a metallic element, and substantially determines a work function for the gate stack over the second portion of the substrate;
forming a second layer of a gate stack over the gate dielectric layer; wherein the second layer comprises a metallic element, and after forming the first layer and forming the second layer, the second layer overlies the first layer over the second portion of the substrate;
implanting a boron-containing species into the second layer wherein after implanting the boron-containing species, the second layer substantially determines a work function of the gate stack over the first portion of the substrate;
forming a third layer of the gate stack after forming the first layer and the second layer;
patterning the gate stack, wherein after patterning the gate stack a first gate electrode overlies the first portion of the substrate and a second gate electrode overlies the second portion of the substrate;
forming a first source/drain region over the first portion of the substrate, wherein after forming the first source/drain region, a first transistor lies over the first portion of the substrate and includes the first source/drain and the first gate electrode; and
forming a second source/drain region over the second portion of the substrate, wherein after forming the second source/drain region, a second transistor lies over the second portion of the substrate and includes the second source/drain and the second gate electrode.
8. The process of claim 7 , wherein the boron-containing species comprises B or BF 2 .
9. The process of claim 8 , wherein the second layer comprises an elemental transition metal, a transition metal nitride, a transition metal silicon nitride, or any combination thereof.
10. The process of claim 7 , further comprising: removing the second layer from the first portion of the substrate before forming the first layer.
11. The process of claim 7 , wherein:
the first transistor is a PMOS transistor;
the first layer lies immediately adjacent to the gate dielectric layer;
the second transistor is an NMOS transistor;
the second layer lies immediately adjacent to the gate dielectric layer; and
the first gate electrode does not include the first layer.
12. The process of claim 11 , wherein forming the third layer is performed before implanting the boron-containing species.
13. The process of claim 1 , wherein the second layer over the first portion of the substrate and the second layer over the second portion of the substrate have substantially the same composition.
14. The process of claim 5 , wherein the PMOS transistor includes a metal-nitride material between the third layer and the gate stack and the gate dielectric layer.
15. The process of claim 1 , wherein the second layer comprises a third element that is a metallic element.
16. The process of claim 15 , wherein the first element is different from the third element.
17. The process of claim 7 , wherein the second layer over the first portion of the substrate and the second layer over the second portion of the substrate have substantially the same composition.
18. The process of claim 9 , wherein the NMOS transistor includes a metal-boride material.
19. The process of claim 18 , wherein the metal boride material lies between the third layer and the gate dielectric layer of the NMOS transistor.
20. The process of claim 7 , wherein the first layer and the second layer each comprise a different metallic element.