IP Library Granted Patent US 7,091,602
Granted Patent B2
US 7,091,602 · App. 10/318,699 · Granted Aug 15, 2006

Miniature moldlocks for heatsink or flag for an overmolded plastic package

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Quick Facts
Patent No.
US 7,091,602
App. No.
10/318,699
Granted
Aug 15, 2006
Kind
B2
Abstract

A system of mold locks ( 28, 30 ) is formed on a heatsink ( 2 ) of a packaged semiconductor to prevent/mitigate delamination. The mold locks ( 4, 12 ) anchor a plastic mold compound ( 34 ) that forms the protective cover for the packaged semiconductor die. The mold locks ( 4, 12 ) are miniaturized to allow the positioning of them within the flag portion of the heatsink ( 2 ) and leadframe ( 24 ) such that a semiconductor die can be anchored above the mold locks ( 4, 12 ) formed within the flag portion of the heatsink/lead frame ( 2, 24 ). The miniaturized size of the said moldlocks ( 4, 12 do not detract from the purpose of the die attach solder ( 36 ).

Claims (34)

1. A microchip structure to prevent delamination, comprising;

a mold lock, comprising:

a primary channel;

a secondary channel formed above said primary channel; and

a dovetail profile protruding into said primary channel from a wall of said primary channel;

a row of said mold locks formed along an outer edge of a heatsink of said microchip structure; and

a pattern of said mold locks formed within a flag area of said heatsink.

2. The microchip structure to prevent delamination of claim 1 , wherein said pattern is a row.

3. The microchip structure of claim 1 , wherein said primary channel has a depth of less than 0.012 inches.

4. The microchip structure of claim 1 , wherein said secondary channel has a depth of less than 0.008 inches.

5. The microchip structure to prevent delamination of claim 1 , wherein said mold locks formed within the flag area of said heatsink are coupled to a plastic mold compound.

6. The microchip structure to prevent delamination of claim 1 , wherein said mold locks formed within the flag area of said heatsink are coupled to a soldering compound.

7. A packaged semiconductor, comprising:

a mold lock having a primary channel and a dovetail profile protruding into said primary channel from a wall of said primary channel;

a heatsink having a row of said mold locks formed along an outer edge of said heatsink and a pattern of said mold locks formed in an interior portion of said heatsink; and

a plastic mold compound coupled to said mold locks formed along the outer edge of said heatsink.

8. The packaged semiconductor of claim 7 , further comprising a secondary channel formed above said primary channel.

9. The packaged semiconductor of claim 8 , wherein said primary channel has a depth of less than 0.012 inches.

10. The packaged semiconductor of claim 9 , wherein said secondary channel has a depth of less than 0.008 inches.

11. The packaged semiconductor of claim 7 , wherein a soldering compound is coupled to said pattern of mold locks.

12. The packaged semiconductor of claim 7 , wherein said plastic mold compound is coupled to said pattern of mold locks.

13. A microchip structure to prevent delamination, comprising;

mold lock means formed in a heatsink to anchor a compound to said heatsink,

wherein said mold lock means comprising:

primary channel means to receive said compound; and

dovetail profile means to anchor said compound to said mold lock means;

a row of said mold lock means formed along an outer edge of said heatsink; and

a pattern of said mold lock means formed within the flag area of said heatsink.

14. The microchip structure to prevent delamination of claim 13 , wherein said pattern is a row.

15. The microchip structure to prevent delamination of claim 13 , wherein said primary channel means has a depth of less than 0.012 inches.

16. The microchip structure to prevent delamination of claim 13 , wherein compound is a plastic.

17. The microchip structure to prevent delamination of claim 13 , wherein said compound is a solder.

18. The microchip structure to prevent delamination of claim 13 , wherein said mold lock means further comprises secondary channel means formed above said primary channel means to form said dovetail profile means.

19. The microchip structure to prevent delamination of claim 18 , wherein said secondary channel means has a depth of less than 0.008 inches.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →