Speedpath repair in an integrated circuit
View Patent ↗A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality of transistors and disposed in parallel with the first plurality of transistors along the speedpath, wherein the second channel length is different from the first channel length. In addition, the circuit comprises an element configured to selectively replace the first plurality of transistors with the second plurality of transistors in response to a determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath. In one embodiment, the second channel length is a sub-minimal geometry with respect to the first channel length.
1. A circuit comprising:
a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance;
a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality of transistors and disposed in parallel with the first plurality of transistors along the speedpath, wherein the second channel length is different from the first channel length; and
means for selectively replacing the first plurality of transistors with the second plurality of transistors in response to a determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath.
2. The circuit of claim 1 , wherein the second channel length is a sub-minimal geometry with respect to the first channel length.
3. The circuit of claim 1 , wherein the selectively replacing means includes
a multiplexer having first and second multiplexer inputs, a multiplexer select input and an output, wherein an output of the first plurality of transistors disposed along the speedpath couples to the first multiplexer input, an output of the second plurality of transistors disposed in parallel along the speedpath couples to the second multiplexer input, and wherein responsive to a first state on the multiplexer select input, the first multiplexer input is coupled to the multiplexer output and responsive to a second state on the multiplexer select input, the second multiplexer input is coupled to the multiplexer output.
4. The circuit of claim 3 , further comprising a fuse, wherein the fuse couples to the multiplexer select input, and wherein the fuse provides one of the first state or the second state on the multiplexer select input as a function of a condition of the fuse.
5. The circuit of claim 4 , wherein the fuse comprises a post-silicon programmable device.
6. The circuit of claim 1 , further comprising:
a switch for disabling the second plurality of transistors in response to the first plurality of transistors meeting the speedpath timing requirement and in order to ensure meeting of a maximum current leakage specification.
7. The circuit of claim 1 , wherein the first plurality of transistors comprise a bitcell of a memory, and wherein the second plurality of transistors comprise a redundant bit cell of the memory.
8. The circuit of claim 7 , further wherein the second plurality of transistors is selected from a group consisting of (i) a p-channel pull-up transistor, (ii) an n-channel pull-down transistor, and (iii) an n-channel pass transistor.
9. The circuit of claim 1 , wherein the circuit comprises a peripheral circuit to a memory and wherein the speedpath is included within the peripheral circuit.
10. The circuit of claim 1 , wherein the circuit includes a plurality of logic elements coupled between a first flip-flop and a second flip-flop, wherein the plurality of logic elements provide a given timing performance, wherein at least one logic element of the plurality of logic elements controls the timing performance of the speedpath.
11. The circuit of claim 10 , wherein the at least one logic element further includes the first plurality of transistors which is selectively replaced by a second logic element that includes the second plurality of transistors.
12. The circuit of claim 10 , wherein the at least one logic element further includes the first plurality of transistors and the second plurality of transistors.
13. The circuit of claim 10 , wherein the at least one logic element includes a logic gate.
14. The circuit of claim 1 , wherein the determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath includes at least one selected from the group consisting of (i) a physical measurement representative of the first channel length exceeding a threshold channel length geometry and (ii) an electrical timing measurement of the first plurality of transistors not meeting or exceeding the speedpath timing requirement.
15. A method of implementing a circuit comprising:
providing a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors characterized by a first timing performance;
providing a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality of transistors and disposed in parallel with the first plurality of transistors along the speedpath, wherein the second channel length is different from the first channel length; and
selectively replacing the first plurality of transistors with the second plurality of transistors in response to a determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath.
16. The method of claim 15 , wherein the second channel length is a sub-minimal geometry with respect to the first channel length.
17. The method of claim 15 , wherein providing the first plurality of transistors comprise a bitcell of a memory, and wherein providing the second plurality of transistors comprises providing a redundant bitcell of the memory.
18. The method of claim 17 , further wherein the step of providing the second plurality of transistors is further characterized by the second plurality of transistors being in a group consisting of (i) a p-channel pull-up transistor, (ii) an n-channel pull-down transistor, and (iii) an n-channel pass transistor.
19. The method of claim 15 , wherein determining that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath includes performing an electrical timing measurement of the first plurality of transistors and wherein the measurement does not meet or exceed the speedpath timing requirement.
20. A circuit having a speedpath, comprising;
first means for performing a function in the speedpath, wherein the first means comprises a first plurality transistors having channel lengths;
second means for performing the function, wherein the second means comprises a second plurality of transistors, wherein each transistor of the second plurality of transistors has a corresponding transistor in the first plurality of transistors, and each transistor of the second plurality of transistors has a shorter channel length than its corresponding transistor; and
replacement means for replacing the first means with the second means if the speedpath does not meet a speed requirement.