Method and system for reducing power consumption in a cache memory
View Patent ↗A method and system are for reducing power consumption in a multi-way set-associative cache memory. During a first clock cycle, in response to an address, an associated set is identified in the cache memory. The address is compared to respective tag portions of blocks in the associated set, and a signal is output in response thereto. During a second clock cycle, in response to the signal indicating a match between one of the blocks and the address, a non-tag portion of the matching block in the associated set is read, while a non-matching block in the associated set is disabled.
1. Apparatus for a Y-way set-associative cache memory (e.g., 32 ) having Y>1 blocks and X>1 sets, wherein each block y, 0≦y≦(Y−1), of each set x, 0≦x≦(X−1), is adapted to store an address tag (e.g., Tag xy ), a state (e.g., State xy ), and Z words (e.g., W xyz ), 0≦z≦(Z−1), the apparatus comprising:
first circuitry (e.g., 130 and 150 ) adapted to (1) receive a fetch address, (2) determine a set associated with the fetch address, (3) read Y address tags and Y states corresponding to the associated set, (4) determine which of the Y address tags are valid based on the Y states, (5) compare the fetch address to one or more valid address tags, and (6) generate, if one of the valid address tags matches the fetch address, a first control signal (e.g., 110 ) indicating that the block associated with the matching valid address tag is a matching block;
second circuitry (e.g., 132 , 138 a - d , and 134 a - d ) adapted to (1) receive the fetch address, (2) receive the first control signal generated by the first circuitry, (3) generate a second control signal (e.g., 126 e ) based on the first control signal and indicating the matching block, (4) generate block-enable control signals (e.g., 126 a - d ) for the cache memory, (5) apply the block-enable control signals to the cache memory, such that the matching block in the cache memory is enabled and the (Y−1) other blocks in the cache memory are at least partly disabled, and (6) apply the fetch address to the cache memory to read one or more associated words from the enabled matching block; and
third circuitry (e.g., 112 ) connected to an output of each block of the cache memory and adapted to (1) receive the second control signal generated by the second circuitry, (2) receive the one or more associated words from the enabled matching block, and (3) select the one or more associated words for output from the cache memory based on the second control signal, wherein:
the first circuitry comprises a first latch (e.g. 130 ) adapted to latch the fetch address;
the second circuitry comprises:
a second latch (e.g. 132 ) adapted to latch the first control signal and output the second control signal; and
a plurality of other latches (e.g., 134 a - d ) adapted to latch the block-enable control signals; and
the third circuitry comprises a multiplexer (e.g. 112 ) adapted to receive the outputs from the blocks and select the one or more associated words from the enabled matching block based on the second control signal from the second latch.
2. The invention of claim 1 , wherein power consumed by each of the (Y−1) at least partly disabled blocks is less than power consumed by the enabled matching block.
3. The invention of claim 1 , wherein:
during a clock cycle k:
the first circuitry (1) receives the fetch address, (2) determines the associated set, (3) reads the Y address tags and the Y states corresponding to the associated set, (4) determines the one or more valid address tags, (5) compares the fetch address to the one or more valid address tags, and (6) generates the first control signal; and
the second circuitry (1) receives the fetch address, (2) receives the first control signal, and (3) generates the block-enable control signals; and
during a next clock cycle k+1:
the second circuitry (1) generates the second control signal, (2) applies the block-enable control signals to the cache memory to enable the matching block and at least partly disable the (Y−1) other blocks and (3) applies the fetch address to the cache memory to read the one or more associated words from the enabled matching block; and
the third circuitry (1) receives the second control signal, (2) receives the one or more associated words from the enabled matching block, and (3) selects the one or more associated words for output from the cache memory based on the second control signal.
4. A method for operating a Y-way set-associative cache memory (e.g., 32 ) having Y>1 blocks and X>1 sets, wherein each block y, 0≦y≦(Y−1), of each set x, 0≦x≦(X−1), stores an address tag (e.g., Tag xy ), a state (e.g., State xy ), and Z words (e.g., W xyz ), 0≦z≦(Z−1), the method comprising:
(1) receiving a fetch address;
(2) determining a set associated with the fetch address;
(3) reading Y address tags and Y states corresponding to the associated set;
(4) determining which of the Y address tags are valid based on the Y states;
(5) comparing the fetch address to one or more valid address tags; and
(6) generating, if one of the valid address tags matches the fetch address, a first control signal (e.g., 110 ) indicating that the block associated with the matching valid address tag is a matching block;
(7) generating block-enable control signals (e.g., 126 a - d ) for the cache memory;
(8) generating a second control signal (e.g., 126 e ) based on the first control signal and indicating the matching block;
(9) applying the block-enable control signals to the cache memory, such that the matching block in the cache memory is enabled and the (Y−1) other blocks in the cache memory are at least partly disabled;
(10) applying the fetch address to the cache memory to read one or more associated words from the enabled matching block; and
(11) selecting the one or more associated words for output from the cache memory based on the second control signal, wherein:
step (1) comprises latching the fetch address;
step (7) comprises latching the block-enable control signals;
step (8) comprises latching the first control signal to output the second control signal; and
step (11) comprises muxing outputs from the blocks to select the one or more associated words from the enabled matching block based on the second control signal.
5. The invention of claim 4 , wherein power consumed by each of the (Y−1) at least partly disabled blocks is less than power consumed by the enabled matching block.
6. The invention of claim 4 , wherein:
a clock cycle k comprises (1) receiving the fetch address, (2) determining the associated set, (3) reading the Y address tags and the Y states corresponding to the associated set, (4) determining the one or more valid address tags, (5) comparing the fetch address to the one or more valid address tags, (6) generating the first control signal, and (7) generating the block-enable control signals; and
a next clock cycle k+1 comprises (8) generating the second control signal, (9) applying the block-enable control signals to the cache memory to enable the matching block and at least partly disable the (Y−1) other blocks, (10) applying the fetch address to the cache memory to read the one or more associated words from the enabled matching block, and (11) selecting the one or more associated words for output from the cache memory based on the second control signal.
7. A Y-way set-associative cache memory (e.g., 32 ) comprising:
Y>1 blocks and X>1 sets, wherein each block y, 0≦y≦(Y−1), of each set x, 0≦x≦(X−1), is adapted to store an address tag (e.g., Tag xy ), a state (e.g., State xy ), and Z words (e.g., W xyz ), 0≦z≦(Z−1);
first circuitry (e.g., 130 and 150 ) adapted to (1) receive a fetch address, (2) determine a set associated with the fetch address, (3) read Y address tags and Y states corresponding to the associated set, (4) determine which of the Y address tags are valid based on the Y states, (5) compare the fetch address to one or more valid address tags, and (6) generate, if one of the valid address tags matches the fetch address, a first control signal (e.g., 110 ) indicating that the block associated with the matching valid address tag is a matching block;
second circuitry (e.g., 132 , 138 a - d , and 134 a - d ) adapted to (1) receive the fetch address, (2) receive the first control signal generated by the first circuitry, (3) generate a second control signal (e.g., 126 e ) based on the first control signal and indicating the matching block, (4) generate block-enable control signals (e.g., 126 a - d ) for the cache memory, (5) apply the block-enable control signals to the cache memory, such that the matching block in the cache memory is enabled and the (Y−1) other blocks in the cache memory are at least partly disabled, and (6) apply the fetch address to the cache memory to read one or more associated words from the enabled matching block; and
third circuitry (e.g., 112 ) connected to an output of each block of the cache memory and adapted to (1) receive the second control signal generated by the second circuitry, (2) receive the one or more associated words from the enabled matching block, and (3) select the one or more associated words for output from the cache memory based on the second control signal, wherein:
the first circuitry comprises a first latch (e.g., 130 ) adapted to latch the fetch address;
the second circuitry comprises:
a second latch (e.g., 132 ) adapted to latch the first control signal and output the second control signal; and
a plurality of other latches (e.g., 134 a - d ) adapted to latch the block-enable control signals; and
the third circuitry comprises a multiplexer (e.g., 112 ) adapted to receive the outputs from the blocks and select the one or more associated words from the enabled matching block based on the second control signal from the second latch.
8. The invention of claim 7 , wherein power consumed by each of the (Y−1) at least partly disabled blocks is less than power consumed by the enabled matching block.
9. The invention of claim 7 , wherein:
during a clock cycle k:
the first circuitry (1) receives the fetch address, (2) determines the associated set, (3) reads the Y address tags and the Y states corresponding to the associated set, (4) determines the one or more valid address tags, (5) compares the fetch address to the one or more valid address tags, and (6) generates the first control signal; and
the second circuitry (1) receives the fetch address, (2) receives the first control signal, and (3) generates the block-enable control signals; and
during a next clock cycle k+1:
the second circuitry (1) generates the second control signal, (2) applies the block-enable control signals to the cache memory to enable the matching block and at least partly disable the (Y−1) other blocks and (3) applies the fetch address to the cache memory to read the one or more associated words from the enabled matching block; and
the third circuitry (1) receives the second control signal, (2) receives the one or more associated words from the enabled matching block, and (3) selects the one or more associated words for output from the cache memory based on the second control signal.