Arrangement and method for digital delay line
View Patent ↗An arrangement ( 100 ) and method for a high precision and low distortion digital delay line with infinite delay. The digital delay line has an oscillating ring ( 110 ) with an odd number of inverting elements that triggers a counter ( 120 ). A comparator ( 130 ) compares the counter and the MSB of a given delay word. A line of inverters ( 150–159 ), double the odd number in the ring oscillator, is connected to a MUX ( 160 ) controlled by the LSB of the delay word. This provides the advantages of: high resolution due to use of a small, basic component, self-delay ring oscillator; small silicon area due to use of a special decoding scheme use the rings number to produce large delays; and easy implementation as a digital block in an integrated circuit using a standard cells library to build the ring and the decoder.
1. A digital delay line arrangement, comprising:
a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value, one of the first and second stages having ring oscillator means, wherein the first stage comprises:
ring oscillator means;
counter means arranged to count oscillations of the ring oscillator means; and
comparator means for comparing the counter means value with the first part of the delay word value to produce the first output signal.
2. A digital delay line arrangement, comprising:
a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
a second stage coupled to receive the first output signal from the stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value,
one of the first and second stages having ring oscillator means; wherein the second stage comprises:
inverter means arranged to receive the first output signal and having a plurality of serially-coupled inverter elements; and
multiplexer means having inputs connected respectively to outputs of predetermined ones of the plurality of inverter elements of the inverter means, having a control input arranged to receive the second part of the delay word value, and having an output for producing the second output signal.
3. A digital delay line arrangement, comprising:
a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value,
one of the first and second stages having ring oscillator means; wherein the first and second parts of the word value are respectively most and least significant parts of the word value.
4. A digital delay line arrangement, comprising:
a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value,
one of the first and second stages having ring oscillator means; wherein the ring oscillator means is arranged to be enabled by a signal to be delayed.
5. The digital delay line arrangement of claim 2 wherein the number of serially-coupled inverter elements in the inverter means is two to the power of the number of bits in the second part of the word value.
6. The digital delay line arrangement of claim 2 , further comprising flip-flop means coupled between the first stage and the second stage.
7. The digital delay line arrangement of claim 6 , wherein the flip- flop means has a data input arranged to receive the first output signal and a clock input arranged to receive the ring oscillator means output.
8. A digital delay line arrangement, comprising:
a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value,
one of the first and second stages having ring oscillator means; wherein the second part of the word value comprises four bits.
9. A digital delay line method, comprising:
providing a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
providing a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value, one of the first and second stages having ring oscillator means: wherein the first stage comprises:
ring oscillator means;
counter means counting oscillations of the ring oscillator means; and
comparator means comparing the counter means value with the first part of the delay word value to produce the first output signal.
10. A digital delay line method, comprising;
providing a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
providing a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value, one of the first and second stages having ring oscillator means; wherein the second stage comprises:
inverter means receiving the first output signal and having a plurality of serially-coupled inverter elements; and
multiplexer means having inputs connected respectively to outputs of predetermined ones of the plurality of inverter elements of the inverter means, having a control input receiving the second part of the delay word value, and having an output producing the second output signal.
11. A digital delay line method, comprising:
providing a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
providing a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value, one of the first and second stages having ring oscillator means; wherein the first and second parts of the word value are respectively most and least significant parts of the word value.
12. A digital delay line method, comprising:
providing a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
providing a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value, one of the first and second stages having ring oscillator means; wherein the ring oscillator means is enabled by a signal to be delayed.
13. The method of claim 10 , wherein the number of serially-coupled inverter elements in the inverter means is two to the power of the number of bits in the second part of the word value.
14. The method of claim 10 , further comprising providing flip-flop means coupled between the first stage and the second stage.
15. The method of claim 14 , wherein the flip-flop means has a data input receiving the first output signal and a clock input receiving the ring oscillator means output.
16. A digital delay line method, comprising:
providing a first stage arranged to produce a first output signal with a delay determined by a first part of a delay word value; and
providing a second stage coupled to receive the first output signal from the first stage and arranged to produce a second output signal with a delay determined by a second part of the delay word value, one of the first and second stages having ring oscillator means; wherein the second part of the word value comprises four bits.