IP Library Granted Patent US 7,238,561
Granted Patent B2
US 7,238,561 · App. 11/195,510 · Granted Jul 3, 2007

Method for forming uniaxially strained devices

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Quick Facts
Patent No.
US 7,238,561
App. No.
11/195,510
Granted
Jul 3, 2007
Kind
B2
Abstract

A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate ( 201 ) with a gate structure ( 209 ) disposed thereon, wherein the gate structure comprises a gate electrode ( 227 ) and at least one spacer structure ( 215, 217 ), and wherein the substrate comprises a first semiconductor material. A first trench ( 231 ) is created in the substrate adjacent to the gate structure through the use of a first etch. The gate electrode is then etched with a second etch. Preferably, the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is d g , the maximum depth of the first and second trenches after the first and second etches is d t , and d g ≧d t .

Claims (26)

1. A method for making a semiconductor device, comprising:

providing a semiconductor structure comprising a substrate with a gate structure disposed thereon, wherein the gate structure comprises a gate electrode and at least one spacer structure, and wherein the substrate comprises a first semiconductor material;

creating a first trench in the substrate through the use of a first etch, the first trench being adjacent to the gate structure; and etching the gate electrode with a second etch, and wherein the first etch is a dry etch, and wherein the second etch is a wet etch.

2. The method of claim 1 , wherein the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is d g , wherein the maximum depth of the first trench after the first and second etches is d t , and wherein d g ≧d t .

3. The method of claim 1 , wherein the first etch primarily etches the substrate, and wherein the second etch primarily etches the gate electrode.

4. The method of claim 1 , further comprising:

epitaxially growing a second semiconductor material in the first trench.

5. The method of claim 4 , wherein the step of epitaxially growing the second semiconductor material on the first semiconductor material also results in the growth of the second semiconductor material on the gate electrode.

6. The method of claim 4 , wherein the maximum height of the gate electrode after the growth of the second semiconductor material is not greater than the maximum height of the gate electrode prior to the first etch.

7. The method of claim 4 , wherein the second semiconductor material has a larger lattice spacing than the first semiconductor material.

8. The method of claim 7 , wherein the first semiconductor material is silicon, and wherein the second semiconductor material is SiGe.

9. The method of claim 1 , further comprising depositing a barrier layer of a first semiconductor material in the first trench.

10. The method of claim 1 , wherein the second etch is conducted in an epitaxial chamber.

11. The method of claim 10 , wherein the second etch comprises treatment with hot gaseous HCl.

12. The method of claim 1 , wherein the first etch also creates a second trench adjacent to the gate structure.

13. The method of claim 1 , wherein the gate electrode is covered with an etch mask during the first etch.

14. The method of claim 1 , wherein the first trench is covered with an etch mask during the second etch.

15. A method for making a semiconductor device, comprising:

providing a semiconductor device comprising a substrate with a gate structure disposed thereon, the gate structure comprising a gate electrode and at least one spacer structure;

creating first and second trenches in the substrate on first and second sides of the gate electrode, respectively, through the use of a first etch; and

etching the gate electrode with a second etch;

wherein the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is d g , wherein the maximum depth of the first and second trenches after the first and second etches is d t , and wherein d g ≧d t .

16. The method of claim 15 , wherein the substrate comprises a first semiconductor material, and further comprising epitaxially growing a second semiconductor material in the first trench.

17. The method of claim 16 , wherein the step of epitaxially growing the second semiconductor material on the first semiconductor material also results in the growth of the second semiconductor material on the gate electrode.

18. The method of claim 15 , wherein the maximum height of the gate electrode after the growth of the second semiconductor material is not greater than the maximum height of the gate electrode prior to the first etch.

19. The method of claim 16 , wherein the first etch is a dry etch, and wherein the second etch comprises treatment with gaseous HCl in an epitaxial chamber.

Assignments (32)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
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To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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