IP Library Granted Patent US 7,514,340
Granted Patent B2
US 7,514,340 · App. 11/368,720 · Granted Apr 7, 2009

Composite integrated device and methods for forming thereof

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Quick Facts
Patent No.
US 7,514,340
App. No.
11/368,720
Granted
Apr 7, 2009
Kind
B2
Abstract

A method for making a composite integrated device includes providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region and is at a surface of the first integrated device. The method further includes forming a sidewall spacer along a sidewall of a first opening in a first dielectric layer, located over the surface of the integrated device, and providing a deformable metal feature adjacent to the sidewall spacer and in the first opening. The method further includes providing a second integrated device having a substrate, an overlying interconnect region, a contact, and a second dielectric layer surrounding the contact of the second integrated device. The method further includes contacting the contact of the second integrated device with the deformable metal feature and pressing the first dielectric layer against the second dielectric layer.

Claims (56)

1. A method for making a composite integrated device, comprising:

providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region;

forming a first dielectric layer over a surface of the first integrated device;

forming a first opening in the first dielectric layer to expose the contact of the first integrated device;

forming a sidewall spacer along a sidewall of the first opening;

providing a deformable metal feature adjacent to the sidewall spacer and in the first opening, so that the deformable metal feature electrically contacts the contact of the first integrated device and extends above the first dielectric layer;

removing the sidewall spacer;

providing a second integrated device having a second substrate, a second overlying interconnect region, a second contact, and a second dielectric layer surrounding the second contact of the second integrated device, wherein the second contact of the second integrated device electrically contacts the second interconnect region of the second integrated device;

contacting the second contact of the second integrated device with the deformable metal feature; and

pressing the first dielectric layer against the second dielectric layer to bring about bonding the second contact of the second integrated circuit to the deformable feature and bonding the second dielectric layer to the first dielectric layer.

2. The method of claim 1 , wherein the step of providing a deformable metal feature further comprises etching back the first dielectric layer to form an opening within the first dielectric layer within which the deformable metal feature is provided.

3. The method of claim 1 , wherein the step of providing a deformable metal feature further comprises:

forming a first metal feature in the opening; and

forming a second metal feature that is over the first metal feature and has a height above the first dielectric layer, wherein the second metal feature is more malleable than the first metal feature.

4. The method of claim 3 , wherein the first metal feature comprises copper and the second metal feature comprises a material selected from a group consisting of indium, tin, gold, silver, bismuth, antimony, and lead.

5. The method of claim 1 , wherein:

the step of removing the sidewall spacer results in an expansion region between the deformable metal feature and the sidewall of the first dielectric layer; and

the step of pressing results in a portion of the deformable metal feature moving into the expansion region.

6. The method of claim 1 , wherein the step of providing the first integrated device further comprises providing an etch stop layer on the surface of the first integrated device.

7. The method of claim 1 , wherein the step of pressing is further characterized as bonding the second contact and bonding the second dielectric layer contemporaneously.

8. The method of claim 1 , wherein the step of providing the second integrated device comprises providing the second contact of the second integrated device as a combination of:

a copper contact to the second interconnect layer; and

a contact feature that is deformable and that contacts the deformable feature of the first integrated device and the copper contact.

9. A method for making a composite integrated device, comprising:

providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region;

forming a first dielectric layer over a surface of the first integrated device;

forming a first opening in the first dielectric layer to expose the contact of the first integrated device;

forming a sidewall spacer along a sidewall of the first opening;

forming a first metal feature having a first melting temperature in the first opening adjacent to the sidewall spacer, so that the first metal feature electrically contacts the contact of the first integrated device;

removing the sidewall spacer;

forming a second metal feature having a second melting temperature lower than the first melting temperature over the first metal feature and having a height above the first dielectric layer;

providing a second integrated device having a second substrate, a second overlying interconnect region, a second contact, and a second dielectric layer surrounding the second contact of the second integrated device, wherein the second contact of the second integrated device electrically contacts the second interconnect region of the second integrated device;

contacting the second contact of the second integrated device with the second metal feature; and

pressing the first dielectric layer against the second dielectric layer to bring about bonding the second contact of the second integrated circuit to the second metal feature and bonding the second dielectric layer to the first dielectric layer.

10. The method of claim 9 , wherein the step of pressing comprises applying heat above the second melting temperature.

11. The method of claim 9 , wherein the first metal feature comprises a material selected from a group consisting of copper and gold and the second metal feature comprises a material selected from a group consisting of indium, tin, bismuth, and lead.

12. The method of claim 9 , wherein the step of pressing causes alloying between the second metal feature and the first metal feature.

13. A method of making a composite integrated device, comprising:

providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region;

forming a first dielectric layer over a surface of the first integrated device;

forming a first opening in the first dielectric layer to expose the contact of the first integrated device;

forming a sidewall spacer along a sidewall of the first opening;

providing a first metal feature that is adjacent to the sidewall spacer and in the first opening and has a height that is below a height of the first dielectric layer;

removing the sidewall spacer;

forming a deformable metal feature that is over the first metal feature and that extends above the height of the first dielectric feature;

providing a second integrated device having a second substrate, a second overlying interconnect region, a second contact, and a second dielectric layer surrounding the second contact of the second integrated device, wherein the second contact of the second integrated device is electrically coupled to the second interconnect region;

contacting the second contact of the second integrated device with the deformable metal feature;

deforming the deformable metal feature so that the first dielectric layer contacts the second dielectric layer; and

bonding the second dielectric layer to the first dielectric layer.

14. The method of claim 13 , wherein the step of deforming the deformable feature causes the deformable feature to bond to the contact of the second integrated device.

15. The method of claim 13 , wherein the step of bonding the second dielectric layer results when the first dielectric layer contacts the second dielectric layer.

16. The method of claim 13 , wherein the step of deforming comprises:

applying heat; and pressing the first integrated device against the second integrated device.

17. The method of 13 , wherein:

the step of removing the sidewall spacer is further characterized as resulting in an expansion region between the deformable region and the sidewall of the first dielectric layer; and

the step of deforming is further characterized as resulting in the expansion region being at least partially filled with a portion of the deformable metal feature.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0823 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Sep 23, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023273/0099 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2006
From: JONES, ROBERT E.; SOMANI, AJAY
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 017641/0564 →