Encryption apparatus and method therefor
View Patent ↗A modified implementation of the Kasumi algorithm executes on a 32-bit processor using full 32-bit operations. The implementation comprises a series of four rounds, each round including an intermediate sub-function executed between two executions of an FL sub-function. The intermediate sub-function is functionally equivalent to two consecutive 16-bit FO sub-functions.
1. A processor-implemented method of operating on a 64-bit plaintext input using a key to produce a 64-bit ciphertext output, the method comprising the steps of:
at the processor, sequentially iterating a round function a number of times using the key to generate the 64-bit ciphertext output, the round function comprising:
obtaining a first 32-bit round function input data block and a second 32-bit round function input data block;
executing an FL sub-function using the first 32-bit round function input data block so as to generate a first interim output data block;
executing an intermediate sub-function using the first interim output data block using the second 32-bit round function input data block so as to generate a second interim output data block, the intermediate sub-function being functionally equivalent to execution of two consecutive 16-bit FO sub-functions, the intermediate sub-function comprising a plurality of exclusive-OR operations using pairs of half-words of data;
executing the FL sub-function using the second interim output data block so as to generate a third 32-bit interim output data block;
performing an exclusive-OR operation on the first 32-bit round function input data block and the third 32-bit interim output data block so as to generate a first 32-bit round function output data block;
using a first intermediate result and a second intermediate result generated by the intermediate sub-function so as to generate a second 32-bit round function output data block; and
providing a 64-bit ciphertext output based on the second 32-bit round function output data block, wherein the number of times of execution of the round function is four, and wherein execution of the FL sub-function is a 32-bit operation.
2. A method as claimed in claim 1 , wherein the 64-bit plaintext input is a concatenation of the first and second 32-bit round function input data blocks.
3. A method as claimed in claim 1 , wherein the first 32-bit round function output data block serves as the first 32-bit round function input data block for a subsequent iteration of the round function and the second 32-bit round function output data block serves as the second 32-bit round function input data block for the subsequent iteration of the round function.
4. A method as claimed in claim 1 , wherein the key is a 128-bit key.
5. A method as claimed in claim 1 , wherein execution of the intermediate sub-function is a 32-bit operation.
6. A method as claimed in claim 1 , wherein the intermediate sub-function comprises a plurality of executions of a 32-bit Fl sub-functions.
7. A method as claimed in claim 6 , wherein each of the 32-bit Fl sub-functions comprises a plurality of S-Box sub-functions arranged to be executable in respect of 32-bit data blocks.
8. A method as claimed in claim 6 , wherein the plurality of exclusive-OR operations are performed between executions of the 32-bit Fl sub-function.
9. A method as claimed in claim 8 , wherein the half-words of data are derived from the first interim output data block, outputs of the 32-bit Fl sub-function and/or the second 32-bit round function input data block.
10. A method as claimed in claim 1 , the method further comprising:
generating KL sub-keys from the key; and
using the KL sub-keys in the FL sub-function.
11. A method as claimed in claim 1 , the method further comprising:
generating KO and KI sub-keys from the key; and
using the KO and KI sub-keys in the 32-bit Fl sub-function.
12. A method as claimed in claim 11 , wherein the KO and KI sub-keys are respectively applied as blocks of 32-bits.
13. A method as claimed in claim 1 , wherein after iterating the round function the number of times, the 64-bit ciphertext output is a concatenation of the first and second 32-bit round function output data blocks.
14. A hardware encryption apparatus for operating on a 64-bit plaintext input using a key to produce a 64-bit ciphertext output, the apparatus comprising a processor arranged to support:
a round function unit which, when executed, uses the key and executable a number of times to generate the 64-bit ciphertext output, the round function block comprising:
a first input which, when executed, receives a first 32-bit round function input data block, and a second input which, when executed, receives a second 32-bit round function input data block;
a first FL sub-function unit which, when executed, performs an FL sub-function in using the 32-bit round function input data block so as to generate a first interim output data block;
an intermediate sub-function unit which, when executed, performs an intermediate sub-function using the first interim output data block using the second 32-bit round function input data block so as to generate a second interim output data block, the intermediate sub-function being functionally equivalent to execution of two consecutive 16-bit FO sub-functions;
a second FL sub-function unit which, when executed, performs the FL sub-function using second interim output data block so as to generate a third 32-bit interim output data block;
an exclusive-OR gate which, when executed, operates on the first 32-bit round function input data block and the third 32-bit interim output data block so as to generate a first 32-bit round function output data block; and
a register which, when executed, stores a second 32-bit round function output data block generated by using a first intermediate result and a second intermediate result generated, when in use, by the intermediate sub-function; and
an output which, when executed, provides the 64-bit ciphertext output based on the second 32-bit round function output data block, wherein the number of times of execution of the round function is four, and wherein execution of the FL sub-function is a 32-bit operation.
15. An apparatus as claimed in claim 14 , wherein the 64-bit plaintext input is a concatenation of the first and second 32-bit round function input data blocks.
16. An apparatus as claimed in claim 14 , wherein the first 32-bit round function output data block serves as the first 32-bit round function input data block for a subsequent iteration of the round function and the second 32-bit round function output data block serves as the second 32-bit round function input data block for the subsequent iteration of the round function.
17. An apparatus as claimed in claim 14 , wherein the intermediate sub-function comprises a plurality of executions of a 32-bit Fl sub-functions.