IP Library Granted Patent US 7,657,682
Granted Patent B2
US 7,657,682 · App. 11/855,706 · Granted Feb 2, 2010

Bus interconnect with flow control

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Quick Facts
Patent No.
US 7,657,682
App. No.
11/855,706
Granted
Feb 2, 2010
Kind
B2
Abstract

A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.

Claims (67)

1. A method of operating a bus interconnect coupled to a plurality of bus masters and a plurality of bus slaves, the method comprising:

receiving a request from a bus master of the plurality of bus masters to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction;

performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold; and

if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.

2. The method of claim 1 wherein:

the resource allocation parameter is an amount of data associated with outstanding bus transactions of a first type requested by the bus master; and

the first threshold is a specific amount of data.

3. The method of claim 2 , wherein the first type of bus transaction is a read transaction and the resource allocation parameter is an amount of data associated with the outstanding read transactions requested by the first bus master.

4. The method of claim 2 , wherein the resource allocation parameter meets the first threshold if the amount of data associated with the outstanding bus transactions is less than or equal to the specific amount of data.

5. The method of claim 1 , wherein:

the first type of bus transaction is a write transaction;

the resource allocation parameter is a number of outstanding write response transactions requested by the first bus master; and

the first threshold is a specific number of outstanding write response transactions associated with the first bus master.

6. The method of claim 1 , wherein:

the transaction ID of the bus transaction is a transaction ID of an outstanding bus transaction requested by the first bus master and the bus transaction's effect on resource usage would allow the resource allocation parameter to meet a second threshold.

7. The method of claim 6 , wherein:

wherein the first type is a read transaction;

the resource allocation parameter is an amount of data requested by outstanding read transactions by the first bus master;

the second threshold is a second specific amount of data; and

wherein the amount of data requested by the read transaction in addition to the amount of data requested by outstanding read transactions by the first master is less than or equal to the second specific amount of data.

8. The method of claim 7 , wherein:

if the data resource allocation parameter allocated to the bus master meets the first threshold, providing a ready signal to the first bus master in an asserted state; and

if the data resource allocation parameter allocated to the bus master does not meet the first threshold, providing the ready signal to the first bus master in a non asserted state and placing the ready signal in an asserted state in response to the receiving the request and a determination that a condition of the first set of at least one condition is met.

9. A bus interconnect comprising:

a first plurality of ports, each port of the first plurality for coupling to a bus master;

a second plurality of ports, each port of the second plurality of ports for coupling to a bus slave;

arbitration circuitry for directing requests from a bus master coupled to a port of the first plurality of ports to a bus slave coupled to a port of the second plurality of ports;

buffer circuitry for buffering information from a bus slave coupled to a port of the second plurality to a bus master coupled to a port of the first plurality of ports; and

flow control circuitry, the flow control circuitry including:

resource allocation circuitry for determining for each bus master coupled to an input port of the first plurality of ports, whether a resource allocation parameter for the bus master meets a threshold for the bus master;

request gating circuitry, the request gating circuitry blocking a request from a bus master coupled to a port of the first plurality of ports if a resource allocation parameter for the bus master does not meet a threshold as determined by the resource allocation circuitry, wherein if the resource allocation parameter is determined not to meet a threshold as determined by the resource allocation circuitry, the request gating circuitry allowing the request only if a transaction ID of the request by the bus master is not a transaction ID of any outstanding bus transactions requested by the bus master of a same type of transaction requested by the request.

10. The bus interconnect of claim 9 , wherein:

the resource allocation parameter is an amount of data associated with outstanding bus transactions of the same type by the bus master making a request, the threshold is a specific amount of data for the bus master.

11. The bus interconnect of claim 10 , wherein the same type of bus transaction is a read transaction and the resource allocation parameter is an amount of data associated with outstanding read transactions requested by a bus master.

12. The bus interconnect of claim 9 , wherein:

the same type of bus transaction is a write transaction,

the resource allocation parameter is a number of outstanding write response transactions requested by a bus master making the request; and

the first threshold is a specific number of outstanding write response transactions associated with the bus master making the request.

13. The bus interconnect of claim 9 , wherein:

the transaction ID of a bus transaction of a request is a transaction ID of an outstanding bus transaction of the same type of a bus master making the request and the bus transaction's effect on resource usage would allow the resource allocation parameter of the bus master to meet a second threshold of the bus master.

14. The bus interconnect of claim 13 , wherein:

the same type is a read transaction;

the resource allocation parameter is an amount of data requested by outstanding read transactions by a bus master making a request;

the second threshold is a second specific amount of data for the bus master; and

wherein the amount of data requested by the read transaction in addition to the amount of data requested by outstanding read transactions by a bus master making the request is less than or equal to the second specific amount of data.

15. The bus interconnect of claim 9 , wherein:

each port of the first plurality of ports includes an output wherein the output is provided in an asserted state to a bus master coupled to the port if the resource allocation parameter for that bus master is determined to meet a threshold for the bus master as determined by the resource allocation circuitry; and

an output of a port of the first plurality of ports is provided in a non asserted state to a bus master coupled to the port if the resource allocation parameter is determined not to meet a threshold for the bus master as determined by the resource allocation circuitry, and if the resource allocation parameter is determined not to meet the threshold for the bus master as determined by the resource allocation circuitry, the port is placed in an asserted state in response to receiving a request from the bus master and a determination that a transaction ID of the request by the bus master is not a transaction ID of any outstanding bus transactions requested by the bus master of a same type of transaction requested by the request.

16. The bus interconnect of claim 9 further comprising:

a first bus master coupled to a first port of the first plurality of ports;

a second bus master coupled to a second port of the first plurality of ports;

a first bus slave coupled to a third port of the second plurality of ports; and

a second bus slave coupled to a fourth port of the second plurality of ports.

17. The bus interconnect of claim 9 , wherein the bus interconnect is compliant with a standard based on the Advance eXtensible Interconnect (AXI) standard.

18. A method of operating a bus interconnect coupled to a plurality of bus masters and a plurality of bus slaves, the method comprising:

receiving a request from a bus master of the plurality of bus masters to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction;

determining if a resource allocation parameter allocated to the bus master meets a first threshold;

performing the transaction if the resource allocation parameter allocated to the bus master meets a first threshold; and

if the resource allocation parameter is determined not meet the first threshold, performing the bus transaction only if:

1) the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the first bus master; or

2) the transaction ID of the bus transaction is a transaction ID of an outstanding bus transaction requested by the first bus master and the bus transaction's effect on resource usage would allow the resource allocation parameter to meet a second threshold.

19. The method of claim 18 , wherein the performing the transaction includes performing the bus transaction as per a standard based on the Advance eXtensible Interconnect (AXI) standard.

20. The method of claim 18 , wherein:

if the data resource allocation parameter allocated to the bus master meets the first threshold, providing a ready signal to the first bus master in an asserted state; and

if the data resource allocation parameter allocated to the bus master does not meet the first threshold, providing the ready signal to the first bus master in a non asserted state and placing the ready signal in an asserted state in response to the receiving the request and one of:

1) the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the first bus master; or

2) the transaction ID of the bus transaction is a transaction ID of an outstanding bus transaction requested by the first bus master and the bus transaction's effect on resource usage would allow the resource allocation parameter to meet a second threshold.

Assignments (29)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
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To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
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