IP Library Granted Patent US 8,760,136
Granted Patent B2
US 8,760,136 · App. 12/660,951 · Granted Jun 24, 2014

Dynamic voltage scaling interface

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Quick Facts
Patent No.
US 8,760,136
App. No.
12/660,951
Granted
Jun 24, 2014
Kind
B2
Abstract

A switcher system or circuit and corresponding methods provide dynamic voltage scaling. One embodiment of an apparatus includes: a switcher controller configured to monitor a signal from a processor for a first state, determine a time that the signal is in the first state, and provide an adjustment signal based on the time, and a power supply coupled to the adjustment signal and configured to provide a variable supply voltage to the processor core, the variable supply voltage controlled by the adjustment signal after the determining a time.

Claims (31)

1. A method of dynamic voltage scaling comprising:

monitoring a dynamic voltage scaling DVS signal for a first state, the DVS signal indicative of a desired change in a supply voltage for a processor;

assessing a time that the DVS signal is in the first state;

providing an adjustment signal to a power supply for real time dynamic adjustments of the supply voltage, wherein the adjustment signal is based on the assessing a time that the DVS signal is in the first state; and

wherein the assessing a time further comprises counting clock edges during the first state.

2. The method of claim 1 wherein the providing an adjustment signal further comprises providing an adjustment signal that is based on the number of clock edges during the first state.

3. The method of claim 2 wherein the adjustment signal that is based on the number of clock edges during the first state is used to incrementally change the supply voltage, wherein the direction of the change is based on the number of clock edges while the DVS signal is in the first state.

4. The method of claim 2 wherein the adjustment signal that is based on the number of clock edges during the first state is used to decrement the supply voltage when the number of clock edges is one, to increment the supply voltage when the number of clock edges is two, and to change the supply voltage to a predefined state when the number of clock edges is three or more.

5. The method of claim 2 wherein the supply voltage is decremented when the number of clock_edges is less than a first count and wherein the supply voltage is incremented when the number of clock edges is greater than a count threshold.

6. The method of claim 1 wherein using the adjustment signal results in the power supply changing by a voltage step, wherein the voltage step is programmable.

7. The method of claim 6 wherein the voltage step is one of a fixed voltage step and a variable voltage step with a first step having a size that varies from a second step.

8. The method of claim 1 wherein the providing an adjustment signal to a power supply is used to adjust the supply voltage from a predefined supply voltage to any of a multiplicity of voltage settings between an upper and a lower limit.

9. The method of claim 1 wherein the providing an adjustment signal to a power supply, wherein the adjustment signal is based on a number of clock edges that occur while the DVS signal is in the first state and wherein the adjustment signal is provided immediately after the number of clock edges is determined and wherein the supply voltage is adjusted at a programmable rate of adjustment.

10. The method of claim 1 wherein the assessing a time and the providing an adjustment signal are performed in hardware with substantially zero latency between the assessing a time and beginning an adjustment of the supply voltage.

11. An integrated circuit with dynamic voltage sealing comprising:

a processor core configured to provide a dynamic voltage scaling (DVS) signal, the DVS signal indicative of a desired change in a supply voltage for the processor core;

a switcher system coupled to the DVS signal and coupled to the processor core and configured to provide a variable supply voltage to the processor core, the switcher system further comprising:

a switcher controller configured to monitor the DVS signal for a first state, determine a time that the DVS signal is in the first state (e.g., see FIGS. 1-5 ), and provide an adjustment signal, wherein the adjustment signal is based on the time that the DVS signal is in the first state,

wherein a power supply coupled to receive the adjustment signal and configured to provide the variable supply voltage, wherein the variable supply voltage begins an adjustment based on the adjustment signal, and

wherein the switcher controller is configured to determine a time that the DVS signal is in the first state by counting clock edges of a clock during the first state.

12. The integrated circuit with dynamic voltage scaling of claim 11 wherein the processor core configured to provide a dynamic voltage scaling (DVS) signal is further configured to provide a DVS signal that is a binary signal, where the time the binary signal is in a first state indicates a direction of change fox the variable supply voltage for the processor.

13. The integrated circuit of claim 11 wherein the switcher controller is configured to provide the adjustment signal, where the adjustment signal is based on a number of clock edges of a clock during the first state.

14. The integrated circuit of claim 13 wherein the switcher controller is configured to use the adjustment signal to incrementally change the variable supply voltage, wherein the direction of the change is based on the number of clock edges of the clock while the DVS signal is in the first state.

15. The integrated circuit of claim 14 wherein the switcher controller is configured to use the adjustment signal to decrement the variable supply voltage when the number of clock edges is a first number and to increment the variable supply voltage when the number of clock edges is a second number.

16. The integrated circuit of claim 15 wherein the switcher controller is further configured to use the adjustment signal to change the variable supply voltage to a predefined state when the number of clock edges is a third number.

17. The integrated circuit of claim 11 wherein the switcher controller further comprises a register and wherein the register includes a voltage step parameter that is programmable and the switcher controller uses the adjustment signal to change the variable supply voltage by the voltage step.

18. The integrated circuit of claim 17 wherein the voltage step is one of a fixed voltage step and a non uniform voltage step.

19. A switcher circuit providing dynamic voltage scaling and comprising:

a switcher controller configured to monitor a signal from a processor for a first state, the signal indicative of a desired change in a variable supply voltage for the processor; to determine a time that the signal is in the first state, and to provide an adjustment signal, wherein the adjustment signal is based on the time that the signal is in the first state, wherein determine a time further comprises counting clock edges during the first state, and

a power supply coupled to the adjustment signal and configured to provide a variable supply voltage to the processor, the variable supply voltage controlled by the adjustment signal after the determine a time that the signal is in the first state.

20. The switcher circuit of claim 19 wherein the switcher controller is configured to use the adjustment signal to decrement the variable supply voltage when the time that the signal is in the first state is a first value and to increment the variable supply voltage when the time that the signal is in the first state is a second value.

Assignments (34)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2025
From: NXP USA, INC.
To: ASCALE TECHNOLOGIES LLC
Reel/Frame 070026/0838 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0194 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0027 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0866 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0120 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024933/0316 →
SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024933/0340 →
SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024915/0759 →
SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024915/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2010
From: LEE, GORDON; CHUN, CHRISTOPHER K.Y.
To: FREESCALE SEMICONDUCTOR, INC.
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