IP Library Granted Patent US 6,884,685
Granted Patent B2
US 6,884,685 · App. 10/366,777 · Granted Apr 26, 2005

Radical oxidation and/or nitridation during metal oxide layer deposition process

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Quick Facts
Patent No.
US 6,884,685
App. No.
10/366,777
Granted
Apr 26, 2005
Kind
B2
Abstract

A metal oxide high-k dielectric is deposited on a semiconductor wafer in a manner that reduces dangling bonds in the dielectric without significantly thickening interfacial oxide thickness. A metal oxide precursor and radical oxygen and/or radical nitrogen are co-flowed over the semiconductor wafer to form the high-k dielectric. The radicals bond to dangling bonds of the metal of the metal oxide during the deposition process that is performed at the regular deposition temperature of less than about 400 degrees Celsius. The radical oxygen and radical nitrogen do not require the higher temperatures generally required in an anneal in order to attach to the dangling bonds of the metal. Thus, a high temperature post deposition anneal, which tends to cause interfacial oxide growth, is not required. The dielectric is of higher quality than is typical because the dangling bonds are removed during deposition rather than after the dielectric has been deposited.

Claims (37)

1. A method of depositing a layer on a semiconductor wafer, comprising:

inserting the semiconductor wafer into a deposition chamber;

flowing a metal oxide precursor as a precursor into the deposition chamber, the metal oxide precursor comprising a compound having both a predetermined metal and oxygen;

while flowing the metal oxide precursor, flowing a radical oxygen gas into the deposition chamber;

heating the metal oxide precursor to form metal oxide bonds over the semiconductor wafer from the predetermined metal and oxygen of the metal oxide precursor; and

using the radical oxygen gas in the deposition chamber to eliminate metal bonds containing an impurity by replacing the impurity with oxygen to form desired metal oxide bonds that deposit to form the layer on the semiconductor wafer.

2. The method of claim 1 , further comprising stopping the flowing of the metal oxide precursor and continuing the flowing of the radical oxygen gas into the deposition chamber to form the layer.

3. The method of claim 1 , wherein the metal oxide precursor is formed by heating a solid and carried by an inert gas.

4. The method of claim 1 , wherein the layer is a gate dielectric comprising a metal oxide.

5. The method of claim 4 , wherein the gate dielectric further comprises nitrogen.

6. The method of claim 5 wherein the metal oxide is selected from hafnium oxide, aluminum oxide, lanthanum oxide, yttrium oxide, and cesium oxide.

7. The method of claim 6 , wherein the metal oxide further comprises silicon.

8. The method of claim 5 , wherein the metal oxide is selected from hafnium aluminum oxide, lanthanum aluminum oxide, yttrium aluminum oxide, and cesium aluminum oxide.

9. The method of claim 5 , wherein the metal oxide is hafnium oxide.

10. The method of claim 9 , wherein the metal oxide precursor comprises heated hafnium tetra-butoxide (HTB) in an inert carrier gas.

11. A method of forming a transistor, comprising:

providing a semiconductor wafer;

inserting the semiconductors wafer into a deposition chamber;

forming a dielectric layer;

completing forming the transistor using the dielectric layer as a gate dielectric;

wherein the forming the dielectric layer comprises:

flowing a metal oxide precursor into the deposition chamber, the metal oxide precursor comprising a compound having both oxygen and a metal, the metal oxide precursor forming metal oxide bonds from components of the compound over the semiconductor wafer in response to heat, some of the metal oxide bonds being dangling bonds;

while flowing the metal oxide precursor, flowing radicals of at least one of oxygen and nitrogen capable of filling dangling bonds of the metal and replacing impurities of the metal oxide bonds with the first element and at a temperature below about 400 degrees Celsius; and

stop flowing the metal oxide precursor and flowing only nitrogen radicals.

12. The method of claim 11 , wherein the metal oxide precursor is either hafnium tetra butoxide (HTB) or TDEAH.

13. The method of claim 11 , wherein the radicals are oxygen radicals.

14. The method of claim 11 , wherein the radicals are only nitrogen radicals.

15. The method of claim 11 , wherein the impurities comprise at least one of hydrogen and carbon.

16. The method of claim 15 , wherein the dielectric layer is a substantially planar layer of substantially uniform thickness.

17. The method of claim 11 , wherein the dielectric layer is a metal oxide selected from hafnium oxide, aluminum oxide, lanthanum oxide, yttrium oxide, and cesium oxide.

18. The method of claim 17 , wherein the dielectric layer further comprises nitrogen.

19. A method of depositing a dielectric layer on a semiconductor wafer, comprising:

inserting the semiconductor wafer into a deposition chamber;

flowing a metal oxide precursor into the deposition chamber, the metal oxide precursor comprising a compound having both a predetermined metal and oxygen, the metal oxide precursor forming metal oxide bonds from components of the metal oxide precursor over the semiconductor wafer in response to being heated, some of the metal oxide bonds containing impurities and some of the metal oxide bonds being dangling bonds; and

while flowing the metal oxide precursor, flowing both a radical oxygen gas and a radical nitrogen gas into the deposition chamber to form the dielectric layer, the radical oxygen gas replacing the impurities and filling the dangling bonds with oxygen atoms, wherein the deposition chamber is heated to a temperature below about 400 degrees Celsius during the flowing.

20. The method of claim 19 , wherein the dielectric layer is a metal oxide further comprising at least one of aluminum, silicon, and nitrogen.

21. The method of claim 19 , wherein the flowing further comprises providing the at least one of the radical oxygen gas and the radical nitrogen gas to the deposition chamber from a location external to the deposition chamber.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
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