Circuits and methods for buffering and communicating data signals
View Patent ↗Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential.
1. A circuit for buffering a data signal to a low voltage logic device, the circuit comprises:
an output buffer having a voltage input configured to receive a supply potential, an input configured to receive the data signal, and having an output, said output buffer configured to produce an output signal based on the data signal, said output signal having a maximum potential;
a first N-type transistor having a source coupled to said output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a predetermined bias potential, said predetermined bias potential greater than said maximum potential and greater than said supply potential; and
at least one diode having a cathode coupled to said gate and having an anode coupled to said source.
2. A circuit according to claim 1 , wherein said first transistor is configured to protect said output buffer at said output when said drain receives a potential greater than said maximum potential.
3. A circuit according to claim 1 , wherein when said drain receives a potential greater than said maximum potential, said first transistor produces an output potential at said source, said output potential equal to or less than said maximum potential.
4. A circuit according to claim 1 , wherein said output buffer comprises:
a second transistor having a source configured to couple to a first potential, a drain coupled to said source of said first transistor, and a gate configured to receive a first signal;
a NAND gate having an input configured to receive the data signal and having an output coupled to said gate of said second transistor, said NAND gate configured to NAND the data signal to produce said first signal;
a third transistor having a drain coupled to said drain of said second transistor and said source of said first transistor, a source configured to couple to a second potential, and a gate configured to receive a second signal; and
a NOR gate having an input configured to receive the data signal and having an output coupled to said gate of said third transistor, said NOR gate configured to NOR the data signal to produce said second signal.
5. A circuit according to claim 4 , wherein said second and third transistors have an operating range, and wherein said maximum potential is based on said operating range.
6. A circuit according to claim 4 , wherein an operating range of the first N-type transistor is greater than operating ranges of the second and third transistors.
7. A circuit according to claim 1 , wherein said output buffer comprises:
a second transistor having a source configured to couple to a first potential, a drain coupled to said source of said first transistor, and a gate configured to receive a first signal;
a third transistor having a drain coupled to said drain of said second transistor and said source of said first transistor, a source, and a gate configured to receive a second signal;
a fourth transistor having a collector coupled to said gate of said third transistor, a base coupled to said source of said third transistor, and an emitter configured to couple to a second potential; and
a resistor having a first terminal coupled to said base of said fourth transistor and said source of said third transistor and having a second terminal coupled to said emitter of said fourth transistor and configured to couple to said second potential.
8. A circuit according to claim 1 , wherein said output buffer comprises:
a second transistor having a source configured to couple to a second potential, a drain coupled to said source of said first transistor, and a gate;
a third transistor having a drain coupled to said drain of said second transistor and said source of said first transistor, a source configured to couple to a second potential, and a gate; and
an operational amplifier having a first input configured to receive the data signal, a second input coupled to said drain of said third transistor, and an output coupled to said gate of said second transistor.
9. A method for communicating a data signal from an output buffer to a low voltage logic device, the output buffer having an operating potential, the method comprising the steps of:
protecting an input of the output buffer via an N-type transistor from receiving a first potential greater than the operating potential, wherein the N-type transistor includes a source, a gate, and a drain, the source is coupled to the input to receive a first supply potential, the drain is configured to receive a second supply potential, and the gate is coupled to a predetermined bias potential that is greater than the first supply potential;
protecting the gate from transient voltages via at least one diode having a cathode coupled to the gate and having an anode coupled to the source; and
buffering the data signal via the output buffer to the low voltage logic device.
10. A method according to claim 9 , wherein said step of protecting the input comprises biasing the gate of the N-type transistor at a third potential greater than the operating potential, and wherein the N-type transistor produces at the input a fourth potential less than or equal to about the operating potential when the drain of the N-type transistor receives the first potential greater than the operating potential.
11. A method for communicating a data signal from an output buffer to a low voltage logic device, the output buffer having an operating potential, the method comprising the steps of:
protecting an output of the output buffer via an N-type transistor from receiving a second potential greater than the operating potential, wherein the N-type transistor includes a source, a gate, and a drain, the source is coupled to the output of the output buffer, the drain is configured to couple to the low voltage logic device, and the gate is coupled to the predetermined bias potential;
protecting the gate from transient voltages via at least one diode having a cathode coupled to the gate and having an anode coupled to the source; and
buffering the data signal via the output buffer to the low voltage logic device.
12. A circuit for buffering a data signal to a low voltage logic device, the circuit comprises:
an output buffer having a voltage input configured to receive a supply potential, an input configured to receive the data signal, and having an output, said output buffer configured to produce an output signal based on the data signal, said output signal having a maximum potential;
an isolation transistor having a source coupled to said output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a predetermined bias potential, said predetermined bias potential greater than said maximum potential and greater than said supply potential; and
at least one diode that includes a cathode coupled to the gate and an anode coupled to the source.
13. A circuit according to claim 12 , wherein the output buffer comprises:
a second transistor having a source configured to couple to a first potential, a drain coupled to the source of the isolation transistor, and a gate configured to receive a first signal;
a NAND gate having an input configured to receive the data signal and having an output coupled to the gate of the second transistor, the NAND gate configured to NAND the data signal to produce the first signal;
a third transistor having a drain coupled to the drain of the second transistor and the source of the isolation transistor, a source configured to couple to a second potential, and a gate configured to receive a second signal; and
a NOR gate having an input configured to receive the data signal and having an output coupled to the gate of the third transistor, the NOR gate configured to NOR the data signal to produce the second signal.
14. A circuit according to claim 13 , wherein an operating range of the isolation transistor is greater than operating ranges of the second and third transistors.
15. A method according to claim 11 , wherein said step of protecting the output comprises biasing the gate of the N-type transistor at a third potential greater than the operating potential, and wherein the N-type transistor produces at the output a fourth potential less than or equal to about the operating potential when the drain of the N-type transistor receives the second potential greater than the operating potential.