IP Library Granted Patent US 6,844,224
Granted Patent B2
US 6,844,224 · App. 10/002,054 · Granted Jan 18, 2005

Substrate contact in SOI and method therefor

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Quick Facts
Patent No.
US 6,844,224
App. No.
10/002,054
Granted
Jan 18, 2005
Kind
B2
Abstract

A doped area is formed in the silicon substrate layer of a silicon-on-insulator stack including a silicon substrate, an insulator layer and an silicon active layer, by implanting a species through at least the insulator layer. In one embodiment, the silicon active layer is etched and the species are implanted in the silicon substrate through the exposed insulator layer. Thus, a doped region is formed in the silicon substrate under the areas where the silicon active layer was removed. In another embodiment after etching the silicon active layer, a dielectric layer is formed adjacent to the silicon active layer and on the insulator layer. In this embodiment, the species are implanted over the entire wafer through both the silicon active layer and the insulator layer. In both embodiments, the species are implanted before forming a gate electrode of a transistor.

Claims (39)

1. A method for forming a contact to a semiconductor substrate of a first conductivity type, comprising:

providing a semiconductor stack including an active layer formed on a first insulator layer and a masking layer over the active layer, wherein the first insulator layer is formed on the semiconductor substrate and wherein the active layer and the masking layer are patterned to have an opening;

implanting the semiconductor substrate through the opening and the first insulator layer with a first species to form a first doped region within the semiconductor substrate, wherein the first doped region is the first conductivity type and is heavily doped, and wherein the masking layer operates as a mask to the implanting;

after the implanting, forming a gate dielectric on the active layer;

forming a gate electrode on the gate dielectric;

forming a source region in the active layer adjacent a first side of the gate electrode;

forming a drain region in the active layer adjacent a second side of the gate electrode, wherein the second side is opposite the first side; and

forming a first contact electrically connected to the first doped region.

2. The method of claim 1 , wherein the first species is p-type.

3. The method of claim 2 , wherein the first species is boron.

4. The method of claim 3 , wherein the implanting uses an energy of approximately 100 KeV.

5. The method of claim 1 , further comprising:

forming an interlayer dielectric layer over the active layer and the first doped region;

etching a first opening in the interlayer dielectric layer;

filling the first opening with a metal to form a second contact electrically connected to the active layer; and

wherein forming a first contact further comprises:

etching a second opening through the interlayer dielectric layer; and filling the second opening with the metal.

6. A method of forming an ohmic contact to a semiconductor substrate of a first conductivity type, comprising:

providing a semiconductor stack including an active layer formed on a first insulator layer, wherein the first insulator layer is formed on the semiconductor substrate;

forming a gate dielectric over the active layer;

forming a gate electrode over the gate dielectric;

forming source and drain regions in the active layer and adjacent the gate electrode as to form a channel region underneath the gate electrode;

removing a portion of the active layer;

forming a second insulator layer adjacent the active layer and on the first insulator layer;

forming a doped region within the substrate before forming the gate electrode and after providing the semiconductor stack, wherein the doped region is the first conductivity type and is sufficiently heavily doped to be able to form the contact;

forming a first opening in the second insulator layer and the first insulator layer; and

forming a conductive material within the first opening.

7. The method of claim 6 , further comprising forming a second opening and filling the second opening to form a contact that is electrically connected to the active layer.

8. The method of claim 6 , wherein the doped region is p-type.

9. The method of claim 8 , wherein the doped region is formed by ion implanting boron at an energy of 100 KeV.

10. The method of claim 6 , wherein the semiconductor stack is silicon-on-insulator.

11. A method of forming a contact to a semiconductor substrate of a first conductivity type, comprising:

providing a semiconductor stack including an active layer formed on a first insulator layer, wherein the first insulator layer is formed on the semiconductor substrate;

removing a portion of the active layer to form an opening in the active layer;

forming a second insulator layer adjacent the active layer and on the first insulator layer;

forming a contact opening in the second insulator layer and the first insulator layer;

forming a conductive material within the contact opening;

forming a doped region within the semiconductor substrate under the area of the opening by implanting through the opening in the active layer before forming the second insulator layer, wherein the doped region is the first conductivity type and is sufficiently heavily doped to be able to form the contact to the conductive material; and

forming a transistor in the active layer after forming the doped region.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Feb 2, 2007
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To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2003
From: MIN, BYOUNG W.
To: MOTOROLA, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2001
From: MIN, BYOUNG W.
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