IP Library Granted Patent US 7,804,283
Granted Patent B2
US 7,804,283 · App. 11/838,696 · Granted Sep 28, 2010

Mode transitioning in a DC/DC converter using a constant duty cycle difference

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Quick Facts
Patent No.
US 7,804,283
App. No.
11/838,696
Granted
Sep 28, 2010
Kind
B2
Abstract

According to an exemplary embodiment, a method includes the step ( 910 ) of driving a buck section of a DC/DC converter with a buck signal that has a buck duty cycle and concurrently with driving the buck section, driving a boost section of the DC/DC converter with a boost signal that has a boost duty cycle, a difference existing between the buck duty cycle and the boost duty cycle. The method also includes the step ( 920 ) of monitoring an input voltage that is coupled to the buck section for a change in the input voltage, and in response to a change in the input voltage, the step ( 930 ) of changing the buck duty cycle and the boost duty cycle such that the difference between the buck duty cycle and the boost duty cycle is substantially constant.

Claims (48)

1. A method of mode transitioning, comprising the steps of:

driving a buck section of a DC/DC converter with a buck signal that has a buck duty cycle that is less than one while the DC/DC converter is in a buck/boost mode of operation;

concurrently with driving the buck section, driving a boost section of the DC/DC converter with a boost signal that has a non-zero boost duty cycle while the DC/DC converter is in the buck/boost mode of operation, a difference existing between the buck duty cycle and the boost duty cycle;

monitoring an input voltage that is coupled to the buck section for a change in the input voltage; and

in response to a change in the input voltage, changing the buck duty cycle and the boost duty cycle such that the difference between the buck duty cycle and the boost duty cycle is substantially constant over substantially an entire range of values of the input voltage that corresponds to the buck/boost mode of operation.

2. The method of claim 1 , wherein the buck duty cycle comprises a first substantially linear function of the input voltage over the range of values.

3. The method of claim 2 , wherein the boost duty cycle comprises a second substantially linear function of the input voltage over the range of values.

4. The method of claim 3 , wherein driving the buck section comprises determining that the input voltage is substantially within the range of values.

5. The method of claim 4 , wherein driving the boost section comprises determining that the input voltage is substantially within the range of values.

6. The method of claim 5 , wherein the first and second substantially linear functions of the input voltage are the same regardless of whether the input voltage has an increasing trend or a decreasing trend.

7. A DC/DC converter, comprising:

a buck section, the buck section configured to receive an input voltage;

an inductor coupled to the buck section;

a boost section coupled to the inductor; and

a controller coupled to the buck and boost sections, the controller configured to monitor the input voltage for a change in the input voltage, and in response to the change in the input voltage, to control a buck duty cycle of the buck section and a boost duty cycle of the boost section during a buck/boost mode of operation such that a difference between the buck duty cycle and the boost duty cycle is substantially constant over substantially an entire range of values of the input voltage corresponding to the buck/boost mode of operation.

8. The DC/DC converter of claim 7 , wherein the buck duty cycle and the boost duty cycle are functions of the input voltage over the range of values.

9. The DC/DC converter of claim 8 , the controller comprising a driving signal generator coupled to the buck and boost sections, the driving signal generator operable to generate a buck driving signal in response to a buck duty cycle signal and a boost driving signal in response to a boost duty cycle signal.

10. The DC/DC converter of claim 9 , the controller further comprising a duty cycle generator coupled to the driving signal generator, the duty cycle generator operable to generate the buck duty cycle signal and the boost duty cycle signal in response to a mode signal and a comp signal.

11. A DC/DC converter, comprising:

a buck section, the buck section configured to receive an input voltage;

an inductor coupled to the buck section;

a boost section coupled to the inductor; and

a controller coupled to the buck and boost sections, the controller configured to drive the buck section and the boost section during a buck/boost mode of operation such that a difference between a buck duty cycle and a boost duty cycle is substantially constant over a range of values of the input voltage, wherein the controller also is configured to drive the buck section and the boost section such that the buck duty cycle and the boost duty cycle are not substantially constant over the range of values of the input voltage, and the buck duty cycle and the boost duty cycle are functions of the input voltage over the range of values, and wherein

the controller comprises

a driving signal generator coupled to the buck and boost sections, the driving signal generator operable to generate a buck driving signal in response to a buck duty cycle signal and a boost driving signal in response to a boost duty cycle signal,

a duty cycle generator coupled to the driving signal generator, the duty cycle generator operable to generate the buck duty cycle signal and the boost duty cycle signal in response to a mode signal and a comp signal, and

a state machine coupled to the duty cycle generator, the state machine operable to generate the mode signal in response to the input voltage and an output voltage.

12. The DC/DC converter of claim 11 , the controller further comprising an error amplifier coupled to the duty cycle generator, the error amplifier operable to generate the comp signal in response to the input voltage and the output voltage.

13. A DC/DC converter circuit for converting an input voltage applied at an input node to an output voltage at an output node, the DC/DC converter comprising:

a buck section coupled to the input node;

an inductor having a first end and a second end, the first end of the inductor coupled to the buck section;

a boost section coupled to a second end of the inductor; and

a controller coupled to the buck section and the boost section, the controller configured to monitor the input voltage for a change in the input voltage, and in response to the change in the input voltage, to control a buck duty cycle of the buck section and a boost duty cycle of the boost section during a buck/boost mode of operation such that a difference between the buck duty cycle and the boost duty cycle is substantially constant over substantially an entire range of values for the input voltage that corresponds to a buck/boost mode of operation of the DC/DC converter.

14. The DC/DC converter of claim 13 , wherein the buck duty cycle and the boost duty cycle are functions of the input voltage over the range of values.

15. The DC/DC converter of claim 13 , the buck section comprising:

a first transistor and a first diode coupled in parallel between the input node and the first end of the inductor; and

a second transistor and a second diode coupled in parallel between the first end of the inductor and a reference voltage.

16. The DC/DC converter of claim 15 , the boost section comprising:

a third transistor and a third diode coupled in parallel between the output node and the second end of the inductor; and

a fourth transistor and a fourth diode coupled in parallel between the second end of the inductor and the reference voltage.

17. The DC/DC converter of claim 16 , wherein a gate of the first transistor is coupled to a node that is operable to receive a first PWM signal having the buck duty cycle, and wherein a gate of the fourth transistor is coupled to a node that operable to receive a second PWM signal having the boost duty cycle.

18. A method of mode transitioning, comprising the steps of:

driving a buck section of a DC/DC converter with a buck signal that has a buck duty cycle while the DC/DC converter is in a buck/boost mode of operation, wherein the buck duty cycle comprises a first linear function of an input voltage over substantially an entire range of values of the input voltage that corresponds to the buck/boost mode of operation;

concurrently with driving the buck section, driving a boost section of the DC/DC converter with a boost signal that has a boost duty cycle while the DC/DC converter is in the buck/boost mode of operation, a difference existing between the buck duty cycle and the boost duty cycle, wherein the boost duty cycle comprises a second linear function of the input voltage over substantially the entire range of values of the input voltage that corresponds to the buck/boost mode of operation;

monitoring an input voltage that is coupled to the buck section for a change in the input voltage; and

in response to a change in the input voltage, changing the buck duty cycle and the boost duty cycle.

19. The method of claim 18 , wherein the difference between the buck duty cycle and the boost duty cycle is maintained to be substantially constant over substantially the entire range of values of the input voltage that corresponds to the buck/boost mode of operation.

20. The method of claim 18 , wherein the first linear function and the second linear function have a same slope direction over substantially the entire range of values of the input voltage that corresponds to the buck/boost mode of operation.

Assignments (26)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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