IP Library Granted Patent US 7,018,747
Granted Patent B2
US 7,018,747 · App. 10/261,905 · Granted Mar 28, 2006

Photomask having line end phase anchors

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Quick Facts
Patent No.
US 7,018,747
App. No.
10/261,905
Granted
Mar 28, 2006
Kind
B2
Abstract

A photomask and a method for making the same in which an opaque feature ( 38 ) is formed on a transparent substrate ( 32 ) and a depression ( 44 ) is etched in the transparent substrate ( 32 ) adjacent to the opaque feature ( 38 ). The depression ( 44 ) is etched to a depth such that a phase difference between light passing through the substrate ( 32 ) outside the depression ( 44 ) and light passing through the depression is 180°. In one embodiment, the depression ( 44 ) is formed in the substrate directly adjacent to an edge of the opaque feature ( 38 ). In another embodiment, the depression ( 58 ) surrounds a mesa structure ( 59 ) formed in the substrate ( 50 ), and the opaque feature ( 62 ) resides on the mesa structure ( 59 ). The depression ( 58 ) may be laterally spaced from an edge of the opaque feature ( 62 ).

Claims (36)

1. A photomask for forming an integrated circuit, comprising:

a light transmissive substrate;

an opaque feature covering a portion of the substrate, wherein the opaque feature has a length and a width wherein the length is greater than the width and wherein the opaque feature corresponds to a feature of the integrated circuit having a length and a width and further wherein the opaque feature length is less than the length of the corresponding integrated circuit feature; and

a depression formed in a portion of the substrate not covered by the feature, but in proximity to an edge of the feature.

2. The photomask of claim 1 , further wherein a depth of the depression produces a phase difference between light passing through the substrate outside the depression and light passing through the depression of 180°.

3. The photomask of claim 1 , wherein the depression defines a mesa structure in the substrate wherein the mesa structure underlies the opaque feature and wherein a width of the mesa structure is substantially equal to a width of the opaque feature.

4. The photomask of claim 3 , wherein an length of the opaque feature is the length of the mesa.

5. The photomask of claim 1 , wherein the opaque feature comprises a chromium-based material and the substrate comprises quartz.

6. The photomask of claim 1 , wherein the depression is positioned at an end of the opaque feature and wherein a width of the depression is substantially equal to a width of the opaque feature.

7. A method for forming a photomask, comprising:

forming an opaque feature having a length and a width on a light transmissive substrate wherein the opaque feature corresponds to a feature of an integrated circuit to be formed using the photomask, and further wherein the length of the opaque feature is less than a length of the corresponding integrated circuit element; and

etching a depression in at least a portion of the substrate not covered by the opaque feature, but in proximity to an edge of the opaque feature.

8. The method of claim 7 , wherein forming the opaque feature comprises:

depositing an opaque material across the substrate;

patterning a first photoresist layer on the opaque material such that an area of the opaque material is exposed;

etching the area of the opaque material exposed by the first photoresist layer to define the feature;

removing the first photoresist layer;

patterning a second photoresist layer on the feature such that an end of the feature is exposed; and

etching the exposed end of the feature, thereby shortening a length of the feature and exposing an area of the substrate.

9. The method of claim 8 , wherein etching the depression in the substrate comprises etching the area of the substrate exposed by the etching of the end of the feature, thereby forming the depression in the substrate directly adjacent to an edge of the feature.

10. The method of claim 7 , wherein etching the depression comprises etching the entire portion of the substrate not covered by the opaque feature.

11. The method of claim 10 , wherein the feature is used as a mask during the etching of the depression in the substrate such that the depression is self-aligned to an edge of the feature.

12. The method of claim 11 , further comprising:

patterning a second photoresist layer on the feature subsequent to the etching of the depression in the substrate, thereby exposing an end of the feature; and

etching the end of the feature exposed by the second photoresist layer such that the depression is laterally spaced from the edge of the patterned feature.

13. The method of claim 7 , wherein the feature comprises a chromium-based material and the substrate comprises quartz.

14. The method of claim 7 , wherein the depression wherein the depression is positioned at an end of the opaque feature and wherein a width of the depression is substantially equal to a width of the opaque feature.

15. A photomask for fabricating an integrated circuit, comprising:

a light transmissive substrate comprising a thick portion having a first thickness and a thinner portion having a second thickness; and

an opaque feature formed on a portion of the thick portion of the substrate, an edge of the opaque feature being in proximity to the thinner portion of the substrate, wherein the opaque feature defines a line corresponding to a line in the integrated circuit and

wherein a length of the opaque feature is shorter than a length of the corresponding integrated circuit line.

16. The photomask of claim 15 , wherein the edge of the opaque feature is directly adjacent to the thin portion of the substrate.

17. The photomask of claim 15 , wherein the edge of the opaque feature is laterally displaced from the thin portion wherein a portion of the thick portion of the substrate at an end of the opaque feature is not covered by the opaque feature.

18. The photomask of claim 15 , wherein the thick portion of the substrate comprises the majority of the substrate and the thin portion of the substrate comprises portions of the substrate in proximity to an end of an opaque feature.

19. The photomask of claim 15 , wherein the thin portion of the substrate comprises substantially all portions of the substrate not covered by the opaque feature.

20. The phototnaak of claim 15 , wherein the thickness difference between the thin portion and the thick portion is approximately equal to (λ/2)/(n−1) where λ is the wavelength of light to which the photomask is exposed and n is the refractive index of the substrate.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2002
From: WU, WEI E.; ROMAN, BERNARD J.
To: MOTOROLA, INC.
Reel/Frame 013356/0019 →