Method and program product for protecting information in EDA tool design views
View Patent ↗Sensitive circuit design information in HDL Interface Logic Models such as module names and structures within certain EDA tool design views is eliminated by substituting selected instance and net names with unrelated unique identifiers prior to transferring the design views as part of a simulation model of a circuit design, and consequently avoiding unauthorized use of that information. The method for encoding signal names in different design views of an IC design includes providing a list of names contained in a plurality of design databases, changing each name in the list of names to a protected name, and substituting each changed name with an associated protected name in each design view database.
1. A method comprising:
scanning a first view of an IC design for instance names and net names that identify one or more logic path within the IC design;
mapping each of one or more names found from scanning to an associated unique identifier dissimilar to its associated name;
replacing, in the first view, one or more occurrences of a mapped name with its associated unique identifier to generate a first protected view of the IC design such that one or more logic path in the IC design is not disclosed in the first protected view;
replacing, in a second or more views of the IC design, one or more occurrences of the mapped name with its associated unique identifier to generate a second protected view of the IC design such that one or more logic path in the IC design is not disclosed in the second protected view.
2. The method of claim 1 , wherein the one or more names are selected from among instance names and net names in the first view.
3. The method of claim 1 , wherein each name represents a hierarchical association between one or more instance names and one or more net names.
4. The method of claim 1 , wherein the first view is an interface logic model.
5. The method of claim 1 , wherein the first and second views are netlists.
6. The method of claim 1 , wherein the first and second views are written in a hardware description language.
7. The method of claim 1 , wherein the second view is coded in Verilog.
8. The method of claim 1 , wherein the first view is formatted in a standard parasitic exchange format.
9. An article of manufacture comprising a machine-readable medium including program logic embedded therein for performing the steps of claim 1 .
10. A system comprising means for performing the steps of claim 1 .
11. A method for encoding signal names in a plurality of databases containing different information, comprising:
providing a list of names contained in a plurality of databases, wherein each database of the plurality of databases comprises different information related to an IC design;
changing each instance name and net name that identify one or more logic path within the IC design in the list of names to a protected name such that one or more logic path in the IC design is not disclosed; and
substituting each changed name with an associated protected name in each database of the plurality of databases such that one or more logic path in the IC design is not disclosed in any database of the plurality of databases.
12. The method of claim 11 , wherein the list of names contain instance names and net names.
13. The method of claim 11 , wherein one or more names in the list of names represents a hierarchical association between one or more instance names and one or more net names.
14. The method of claim 11 , wherein the plurality of databases include interface logic models.
15. The method of claim 11 , wherein plurality of databases include netlists.
16. The method of claim 11 , wherein the plurality of databases are written in a hardware description language.
17. The method of claim 11 , wherein at least one of the databases of the plurality of databases is formaffed in a standard parasitic exchange format.
18. The method of claim 11 , wherein at least one of the plurality of databases is coded in Verilog.
19. An article of manufacture comprising a machine-readable medium including program logic embedded therein for performing the steps of claim 11 .
20. A system comprising means for performing the steps of claim 11 .