Electronic device testing system
View Patent ↗A method and system for testing an electronic device is disclosed. The method includes loading a first test into a test pattern generator of a first device and generating a first test pattern at the test pattern generator. A second test seed is loaded into the test pattern generator while the first test pattern is being generated. In one embodiment, the state of the test pattern generator is modified based upon the second test seed, and the first test seed.
1. A method, comprising:
generating a first test pattern at a test pattern generator based on a first test seed, the test pattern generator comprising a first register comprising a first plurality of latches and a linear feedback shift register (LFSR);
pre-loading a second test seed into the first register of the test pattern generator while the first test pattern is being generated;
modifying a state of the LFSR based on the second test seed by applying an exclusive OR operation to the state of the LFSR and to data stored at each of the first plurality of latches while the first test pattern is being generated.
2. The method of claim 1 , wherein LFSR comprises:
a plurality of XOR gates, each of the plurality of XOR gates comprising an input coupled to an output of a corresponding latch of the first plurality of latches; and
a second plurality of latches, each of the second plurality of latches comprising an input coupled to an output of a corresponding one of the plurality of XOR gates.
3. The method of claim 2 , further comprising:
generating a second test pattern at the LFSR based on the second test seed; and
pre-loading a third test seed into the test pattern generator while the second test pattern is being generated.
4. The method of claim 3 , further comprising modifying the state of the LFSR based on the third test seed by applying an exclusive OR operation to data stored at each of the first plurality of latches while the second test pattern is being generated.
5. The method of claim 3 , further comprising:
generating the second test pattern at the LFSR after generating the first test pattern, the second test pattern based on a last state of the LSFR and the second test seed.
6. The method of claim 3 , wherein the second test seed was derived to provide a predetermined second test pattern.
7. The method of claim 6 , wherein the second test seed is based upon an expected state of the test pattern generator.
8. The method of claim 6 , wherein the second test seed is derived based on a Gaussian-Jordan elimination method.
9. The method of claim 1 , wherein the first test pattern is generated at a first semiconductor device and further comprising:
providing the first test pattern to a second semiconductor device, the second semiconductor device formed at a different substrate than the first semiconductor device.
10. The method of claim 1 , wherein the first test pattern is generated at a first semiconductor device and further comprising:
providing the first test pattern to a second semiconductor device, the second semiconductor device formed at a same substrate as the first semiconductor device.
11. A method, comprising:
generating a first test pattern at a test pattern generator based on a first test seed;
pre-loading a second test seed into the test pattern generator while the first test pattern is being generated, the second test seed derived to generate a predetermined test pattern at the test pattern generator;
wherein the second test seed was derived by testing a first device using a first plurality of pseudo-random test patterns generated using a linear feedback shift register (LFSR) using a first set of seed values to generate a first set of test results;
determining a first test pattern based on the first set of test results; and
determining a second set of seed values to generate the first test pattern using the LFSR.
12. The method of claim 11 , wherein the first test pattern is further generated based on the first test seed and the second test seed.
13. The method of claim 11 , wherein the first test pattern is further generated based on a third test seed.
14. The method of claim 11 , wherein the test pattern generator includes a linear feedback shift register (LFSR).
15. The method of claim 11 , further comprising:
modifying a state of the LFSR based on the second test seed;
generating a second test pattern at the LFSR based on the modified state of the LFSR; and
pre-loading a third test seed into the test pattern generator while the second test pattern is being generated.
16. The method of claim 15 , further comprising:
generating the second test pattern at the LFSR after generating the first test pattern, the second test pattern based on a last state of the LSFR and the second test seed.